library ieee;
use ieee.std_logic_1164.all;

entity top is port(
	OTG_D : inout std_logic_vector(31 downto 0);
	OTG_A : out std_logic_vector(17 downto 1);
	OTG_CS_n : out std_logic;
	OTG_WE_n : out std_logic;
	OTG_OE_n : out std_logic;
	OTG_HC_IRQ : in std_logic;
	OTG_DC_IRQ : in std_logic;
	OTG_RESET_n : out std_logic;
	OTG_HC_DREQ : in std_logic;
	OTG_HC_DACK : out std_logic;
	OTG_DC_DREQ : in std_logic;
	OTG_DC_DACK : out std_logic;

	OSC1_50 : in std_logic
	);
end;

architecture arch_top of top is
	signal input_data : std_logic_vector(31 downto 0);
	signal input_wanted : std_logic;
	signal result_ready : std_logic;
	signal result : std_logic_vector(31 downto 0);
	signal want_result : std_logic;
	signal input_ready : std_logic;

component usb_portmux
	port(
	input_data : out std_logic_vector(31 downto 0);
	input_wanted : in std_logic;
	result_ready : in std_logic;
	result : in std_logic_vector(31 downto 0);
	want_result : out std_logic;
	input_ready : out std_logic;

	OTG_D : inout std_logic_vector(31 downto 0);
	OTG_A : out std_logic_vector(17 downto 1);
	OTG_CS_n : out std_logic;
	OTG_WE_n : out std_logic;
	OTG_OE_n : out std_logic;
	OTG_HC_IRQ : in std_logic;
	OTG_DC_IRQ : in std_logic;
	OTG_RESET_n : out std_logic;
	OTG_HC_DREQ : in std_logic;
	OTG_HC_DACK : out std_logic;
	OTG_DC_DREQ : in std_logic;
	OTG_DC_DACK : out std_logic;

	reset_n : in std_logic;
	OSC1_50 : in std_logic;
	clk : in std_logic);
end component;


component summer
	port(
	clk : in std_logic;
	input_data : in std_logic_vector(31 downto 0);
	input_wanted : out std_logic;
	result_ready : out std_logic;
	result : out std_logic_vector(31 downto 0);
	want_result : in std_logic;
	reset : in std_logic;
	input_ready : in std_logic
	);
end component;

signal reset_n : std_logic;
signal reset : std_logic;

begin

reset_n <= '1';
reset <= '0';

usb_portmux_inst: usb_portmux port map (
	input_data,
	input_wanted,
	result_ready,
	result,
	want_result,
	input_ready,

	OTG_D,
	OTG_A,
	OTG_CS_n,
	OTG_WE_n,
	OTG_OE_n,
	OTG_HC_IRQ,
	OTG_DC_IRQ,
	OTG_RESET_n,
	OTG_HC_DREQ,
	OTG_HC_DACK,
	OTG_DC_DREQ,
	OTG_DC_DACK,

	reset_n,
	OSC1_50,
	OSC1_50);

summer_inst: summer port map (
	OSC1_50,
	input_data,
	input_wanted,
	result_ready,
	result,
	want_result,
	reset,
	input_ready
	);

end arch_top;
