module counter (
   input   clk,
   input   reset,

   output reg [31:0] result,
   output reg count_ready,
   input want_count);

   reg [31:0] count;

   always @(posedge clk or posedge reset) begin
      if(reset) begin
         count <= 0;
         count_ready <= 0;
         result <= 0;
      end
      else begin

         if(count_ready && want_count) begin
            count_ready <= 0;
            count <= count + 1;
         end

         else begin
            result <= count;
            count_ready <= 1;
         end
      end
   end

endmodule
