library ieee;
use ieee.std_logic_1164.all;

entity top is port(
	OTG_D : inout std_logic_vector(31 downto 0);
	OTG_A : out std_logic_vector(17 downto 1);
	OTG_CS_n : out std_logic;
	OTG_WE_n : out std_logic;
	OTG_OE_n : out std_logic;
	OTG_HC_IRQ : in std_logic;
	OTG_DC_IRQ : in std_logic;
	OTG_RESET_n : out std_logic;
	OTG_HC_DREQ : in std_logic;
	OTG_HC_DACK : out std_logic;
	OTG_DC_DREQ : in std_logic;
	OTG_DC_DACK : out std_logic;

	OSC1_50 : in std_logic
	);
end;

architecture arch_top of top is
	signal count_ready : std_logic;
	signal result : std_logic_vector(31 downto 0);
	signal want_count : std_logic;

component usb_portmux
	port(
	result : in std_logic_vector(31 downto 0);
	count_ready : in std_logic;
	want_count : out std_logic;

	OTG_D : inout std_logic_vector(31 downto 0);
	OTG_A : out std_logic_vector(17 downto 1);
	OTG_CS_n : out std_logic;
	OTG_WE_n : out std_logic;
	OTG_OE_n : out std_logic;
	OTG_HC_IRQ : in std_logic;
	OTG_DC_IRQ : in std_logic;
	OTG_RESET_n : out std_logic;
	OTG_HC_DREQ : in std_logic;
	OTG_HC_DACK : out std_logic;
	OTG_DC_DREQ : in std_logic;
	OTG_DC_DACK : out std_logic;

	reset_n : in std_logic;
	OSC1_50 : in std_logic;
	clk : in std_logic);
end component;


component counter
	port(
	clk : in std_logic;
	reset : in std_logic;
	count_ready : out std_logic;
	want_count : in std_logic;
	result : out std_logic_vector(31 downto 0)
	);
end component;

signal reset_n : std_logic;

begin

reset_n <= '1';

usb_portmux_inst: usb_portmux port map (
	result,
	count_ready,
	want_count,

	OTG_D,
	OTG_A,
	OTG_CS_n,
	OTG_WE_n,
	OTG_OE_n,
	OTG_HC_IRQ,
	OTG_DC_IRQ,
	OTG_RESET_n,
	OTG_HC_DREQ,
	OTG_HC_DACK,
	OTG_DC_DREQ,
	OTG_DC_DACK,

	reset_n,
	OSC1_50,
	OSC1_50);

counter_inst: counter port map (
	OSC1_50,
	not reset_n,
	count_ready,
	want_count,
	result
	);

end arch_top;
