module summer (
   input   clk,
   input   reset,

   input signed [31:0] input_data,
   input input_ready,
   output reg input_wanted,

   output reg signed [31:0] result,
   output reg result_ready,
   input want_result);

   reg signed [31:0] sum;
   reg signed [31:0] delay;

   parameter DELAY_COUNT = 1;

   always @(posedge clk or posedge reset) begin
      if(reset) begin
         sum <= 0;
         delay <= 0;
      end

      else begin
         result <= sum;
         result_ready <= 1;
   
         if(want_result)
            sum <= 0;
   
         if(delay == 0)
            input_wanted <= 1;
         else
            delay <= delay - 1;
   
         if(input_ready && input_wanted) begin
            sum <= sum + input_data;
            delay <= DELAY_COUNT;
            input_wanted <= 0;
         end
      end
   end

endmodule
