# TCL File Generated by Component Editor 11.1sp2
# Wed Mar 07 23:10:09 EST 2012
# DO NOT MODIFY


# +-----------------------------------
# | 
# | ISP1761 "ISP1761 Interface" v1.0
# | Richard Chang 2012.03.07.23:10:09
# | ISP1761 Interface
# | 
# | E:/Stuff/Project/usbports/usb_portmux/usb_control/ip/isp1761_if/ISP1761_IF.v
# | 
# |    ./ISP1761_IF.v syn, sim
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 11.0
# | 
package require -exact sopc 11.0
# | 
# +-----------------------------------

# +-----------------------------------
# | module ISP1761
# | 
set_module_property DESCRIPTION "ISP1761 Interface"
set_module_property NAME ISP1761
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Terasic Technologies Inc."
set_module_property AUTHOR "Richard Chang"
set_module_property DISPLAY_NAME "ISP1761 Interface"
set_module_property TOP_LEVEL_HDL_FILE isp1761_if.v
set_module_property TOP_LEVEL_HDL_MODULE ISP1761_IF
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
set_module_property FIX_110_VIP_PATH false
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file isp1761_if.v {SYNTHESIS SIMULATION}
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point usb
# | 
add_interface usb conduit end

set_interface_property usb ENABLED true

add_interface_port usb CS_N export Output 1
add_interface_port usb WR_N export Output 1
add_interface_port usb RD_N export Output 1
add_interface_port usb D export Bidir 32
add_interface_port usb A export Output 17
add_interface_port usb DC_IRQ export Input 1
add_interface_port usb DC_DREQ export Input 1
add_interface_port usb HC_DREQ export Input 1
add_interface_port usb DC_DACK export Output 1
add_interface_port usb HC_DACK export Output 1
add_interface_port usb HC_IRQ export Input 1
add_interface_port usb RESET_N export Output 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point slave
# | 
add_interface slave avalon end
set_interface_property slave addressAlignment NATIVE
set_interface_property slave addressUnits WORDS
set_interface_property slave associatedClock clk
set_interface_property slave associatedReset reset
set_interface_property slave bitsPerSymbol 8
set_interface_property slave burstOnBurstBoundariesOnly false
set_interface_property slave burstcountUnits WORDS
set_interface_property slave explicitAddressSpan 0
set_interface_property slave holdTime 10
set_interface_property slave linewrapBursts false
set_interface_property slave maximumPendingReadTransactions 0
set_interface_property slave readLatency 0
set_interface_property slave readWaitStates 30
set_interface_property slave readWaitTime 30
set_interface_property slave setupTime 10
set_interface_property slave timingUnits Nanoseconds
set_interface_property slave writeWaitStates 20
set_interface_property slave writeWaitTime 20

set_interface_property slave ENABLED true

add_interface_port slave s_address address Input 18
add_interface_port slave s_write_n write_n Input 1
add_interface_port slave s_writedata writedata Input 32
add_interface_port slave s_read_n read_n Input 1
add_interface_port slave s_readdata readdata Output 32
add_interface_port slave s_cs_n chipselect_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point slave_irq
# | 
add_interface slave_irq interrupt end
set_interface_property slave_irq associatedAddressablePoint slave
set_interface_property slave_irq associatedClock clk

set_interface_property slave_irq ENABLED true

add_interface_port slave_irq s_irq irq Output 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clk
# | 
add_interface clk clock end
set_interface_property clk clockRate 50000000

set_interface_property clk ENABLED true

add_interface_port clk s_clk clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point reset
# | 
add_interface reset reset end
set_interface_property reset associatedClock clk
set_interface_property reset synchronousEdges DEASSERT

set_interface_property reset ENABLED true

add_interface_port reset s_reset_n reset_n Input 1
# | 
# +-----------------------------------
