<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="System" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element $${FILENAME}
   {
   }
   element ISP1761
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
   element clk
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
   }
   element cpu
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element mem
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VERILOG, output_directory=/autofs/seth.eecg/jayar.i/tm4/src/usbports/usb_portmux/sopc_sys}";
         type = "String";
      }
   }
   element ports
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
   }
   element mem.s1
   {
      datum _lockedAddress
      {
         value = "0";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "4194304";
         type = "long";
      }
   }
   element mem.s2
   {
      datum baseAddress
      {
         value = "4194304";
         type = "long";
      }
   }
   element ISP1761.slave
   {
      datum baseAddress
      {
         value = "0";
         type = "long";
      }
   }
   element ports.slave
   {
      datum baseAddress
      {
         value = "1056768";
         type = "long";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="AUTO" />
 <parameter name="device" value="" />
 <parameter name="deviceFamily" value="STRATIXIV" />
 <parameter name="deviceSpeedGrade" value="" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="maxAdditionalLatency" value="0" />
 <parameter name="projectName" value="usb_control.qpf" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="1" />
 <parameter name="timeStamp" value="1331262202401" />
 <parameter name="useTestBenchNamingPattern" value="false" />
 <instanceScript></instanceScript>
 <interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end">
  <port name="reset_n" internal="reset_n" />
 </interface>
 <interface name="clk" internal="clk.clk_in" type="clock" dir="end">
  <port name="clk" internal="in_clk" />
 </interface>
 <interface name="usb" internal="ISP1761.usb" type="conduit" dir="end">
  <port name="CS_N_from_the_ISP1761" internal="CS_N" />
  <port name="WR_N_from_the_ISP1761" internal="WR_N" />
  <port name="RD_N_from_the_ISP1761" internal="RD_N" />
  <port name="D_to_and_from_the_ISP1761" internal="D" />
  <port name="A_from_the_ISP1761" internal="A" />
  <port name="DC_IRQ_to_the_ISP1761" internal="DC_IRQ" />
  <port name="DC_DREQ_to_the_ISP1761" internal="DC_DREQ" />
  <port name="HC_DREQ_to_the_ISP1761" internal="HC_DREQ" />
  <port name="DC_DACK_from_the_ISP1761" internal="DC_DACK" />
  <port name="HC_DACK_from_the_ISP1761" internal="HC_DACK" />
  <port name="HC_IRQ_to_the_ISP1761" internal="HC_IRQ" />
  <port name="RESET_N_from_the_ISP1761" internal="RESET_N" />
 </interface>
 <interface name="portmux" internal="ports.export" type="conduit" dir="end">
  <port name="m_we_from_the_ports" internal="m_we" />
  <port name="m_re_from_the_ports" internal="m_re" />
  <port name="m_writedata_from_the_ports" internal="m_writedata" />
  <port name="m_readdata_to_the_ports" internal="m_readdata" />
  <port name="m_reset_n_from_the_ports" internal="m_reset_n" />
  <port name="m_address_from_the_ports" internal="m_address" />
 </interface>
 <module kind="clock_source" version="11.1" enabled="1" name="clk">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   kind="altera_avalon_onchip_memory2"
   version="11.1"
   enabled="1"
   name="mem">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="autoInitializationFileName" value="usb_control_mem" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="dataWidth" value="32" />
  <parameter name="deviceFamily" value="Stratix IV" />
  <parameter name="dualPort" value="true" />
  <parameter name="initMemContent" value="true" />
  <parameter name="initializationFileName" value="firmware" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="6144" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="true" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module kind="ISP1761" version="1.0" enabled="1" name="ISP1761">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
 </module>
 <module kind="usb_portmux_iface" version="1.0" enabled="1" name="ports">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
 </module>
 <module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu">
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="setting_preciseDivisionErrorException" value="false" />
  <parameter name="setting_performanceCounter" value="false" />
  <parameter name="setting_illegalMemAccessDetection" value="false" />
  <parameter name="setting_illegalInstructionsTrap" value="false" />
  <parameter name="setting_fullWaveformSignals" value="false" />
  <parameter name="setting_extraExceptionInfo" value="false" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_debugSimGen" value="false" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="setting_bhtIndexPcOnly" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_allowFullAddressRange" value="false" />
  <parameter name="setting_activateTrace" value="true" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="setting_activateModelChecker" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="muldiv_divider" value="false" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="manuallyAssignCpuID" value="false" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_embeddedPLL" value="true" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="dcache_omitDataMaster" value="false" />
  <parameter name="cpuReset" value="false" />
  <parameter name="is_hardcopy_compatible" value="false" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="resetOffset" value="0" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="cpuID" value="0" />
  <parameter name="cpuID_stored" value="0" />
  <parameter name="breakOffset" value="32" />
  <parameter name="userDefinedSettings" value="" />
  <parameter name="resetSlave" value="mem.s1" />
  <parameter name="mmu_TLBMissExcSlave" value="" />
  <parameter name="exceptionSlave" value="mem.s1" />
  <parameter name="breakSlave" value="mem.s1" />
  <parameter name="setting_perfCounterWidth" value="32" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="setting_branchPredictionType" value="Automatic" />
  <parameter name="setting_bhtPtrSz" value="8" />
  <parameter name="muldiv_multiplierType" value="DSPBlock" />
  <parameter name="mpu_minInstRegionSize" value="12" />
  <parameter name="mpu_minDataRegionSize" value="12" />
  <parameter name="mmu_uitlbNumEntries" value="4" />
  <parameter name="mmu_udtlbNumEntries" value="6" />
  <parameter name="mmu_tlbPtrSz" value="7" />
  <parameter name="mmu_tlbNumWays" value="16" />
  <parameter name="mmu_processIDNumBits" value="8" />
  <parameter name="impl" value="Fast" />
  <parameter name="icache_size" value="0" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="icache_numTCIM" value="1" />
  <parameter name="icache_burstType" value="None" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="debug_level" value="NoDebug" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dcache_size" value="0" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dcache_numTCDM" value="1" />
  <parameter name="dcache_lineSize" value="32" />
  <parameter name="instAddrWidth" value="1" />
  <parameter name="dataAddrWidth" value="21" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="23" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="23" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="instSlaveMapParam" value="" />
  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='ISP1761.slave' start='0x0' end='0x100000' /><slave name='ports.slave' start='0x102000' end='0x102040' /></address-map>]]></parameter>
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="deviceFamilyName" value="Stratix IV" />
  <parameter name="internalIrqMaskSystemInfo" value="0" />
  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x400000' end='0x401800' /></address-map>]]></parameter>
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x400000' end='0x401800' /></address-map>]]></parameter>
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
 </module>
 <connection kind="clock" version="11.1" start="clk.clk" end="cpu.clk" />
 <connection kind="clock" version="11.1" start="clk.clk" end="mem.clk1" />
 <connection
   kind="avalon"
   version="11.1"
   start="cpu.data_master"
   end="ISP1761.slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
 <connection
   kind="avalon"
   version="11.1"
   start="cpu.data_master"
   end="ports.slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00102000" />
 </connection>
 <connection kind="clock" version="11.1" start="clk.clk" end="mem.clk2" />
 <connection
   kind="avalon"
   version="11.1"
   start="cpu.tightly_coupled_instruction_master_0"
   end="mem.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00400000" />
 </connection>
 <connection
   kind="avalon"
   version="11.1"
   start="cpu.tightly_coupled_data_master_0"
   end="mem.s2">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00400000" />
 </connection>
 <connection kind="reset" version="11.1" start="clk.clk_reset" end="mem.reset1" />
 <connection kind="reset" version="11.1" start="clk.clk_reset" end="mem.reset2" />
 <connection kind="reset" version="11.1" start="clk.clk_reset" end="ISP1761.reset" />
 <connection kind="reset" version="11.1" start="clk.clk_reset" end="ports.reset" />
 <connection kind="reset" version="11.1" start="clk.clk_reset" end="cpu.reset_n" />
 <connection kind="clock" version="11.1" start="clk.clk" end="ISP1761.clk" />
 <connection kind="clock" version="11.1" start="clk.clk" end="ports.clk" />
</system>
