Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect


This paper examines the electrical design of FPGA interconnect circuitry. We explore the circuit design of pass transistor and tri-state buffer routing switches, determine which transistor sizing, metal width and metal spacing are best for FPGA interconnect, and show that FPGA interconnect should be electrically heterogeneous -- some (~20%) of the routing tracks should be designed for maximum speed while the remainder should be more area-efficient.

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