Sample Placement and Routing

These pictures are of the MCNC benchmark circuit e64. This is one of the smallest circuits I use to benchmark FPGAs -- it contains 230 four-input look-up tables. It is, however, faster to download pictures from a circuit this size than from a larger one, and e64 is still large enough to be interesting.

Initial Random Placement

[Initial Placement]

Final Placement

[Final Placement]

Completely (Detailed) Routed Circuit

The minimum channel width for successful routing was 7; that's the routing shown here. I've highlighted one block (in green) by clicking on it -- its fanout is shown in red, and its fanin is shown in blue.

[Final Routing]

Close-up View of the FPGA Routing Architecture

This picture shows the various wire segments and potential connections between wire segments and logic block pins, etc. I selected the green block; the routing of its fanout is highlighted in red and the routing of its inputs is highlighted in blue.

[Routing Close-up]

Globally Routed Circuit

The pictures above show the results when VPR performs combined global and detailed routing of an FPGA, while the picture below shows how VPR can perform only global routing if that's what you want. Note that global routing required only 6 tracks per channel, while doing a complete (global + detailed) routing required 7 tracks per channel.

[Routing Close-up]

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