The soft processors (processor built using the programmable FPGA fabric) offered by FPGA vendors provide an easy way to "program" an FPGA, but their limited performance necessitates the use of laborious manual hardware design to meet tight area/performance/power constraints. By improving soft processors we aim to capture more of the design in the easier flow, hence simplifying FPGA design. Our recent work added vector extensions to soft processors, we further improve that design by enabling simultaneous execution of vector instructions.

Peter Yiannacouras is currently a PhD candidate in ECE. He received MASc from University of Toronto, ECE, and BASc from University of Toronto, Engineering Science. He has Interned at Intel.

FPGAs are increasingly used in computing as customized soft-processors and accelerators. These designs require memories with multiple ports to effectively share information between computing units. Such memories are normally implemented on FPGAs using their built-in memory blocks, called Block RAMs, but which only provide two ports. Designers have worked around this limitation by using a range of ad-hoc solutions in combination such as banking, "multipumping", and replication. In this work, we measure this design space thoroughly for the first time. We propose approaches to efficiently implement multi-ported register files constructed from Block RAMs and general FPGA logic over a design space which spans direct 'drop-in' solutions to more complex schemes which affect instruction scheduling. The preliminary results show promising scalability and performance for register files with three to 24 ports providing two to 256 elements.

After kicking around in industry for a while, Eric LaForest obtained his Bachelor of Independent Studies in 2007 from the University of Waterloo, studying second-generation stack computer architecture. He began his MASc in Computer Engineering at Toronto in September 2007, where he investigates aspects of FPGA soft-processor architecture under the direction of Prof. Greg Steffan. Eric plans to begin a PhD in the Fall of 2009. His other interests include message-passing concurrency, higher-order functions in programming, and asynchronous circuits.

There is a growing desire within the FPGA community to utilize multi-core hardware to improve the runtime of FPGA CAD software. Current implementations acquire modest speedup using parallel specific algorithms carefully developed by teams of engineers over significant periods of time. Our goal is to parallelize the most significant portion of the FPGA CAD process, the placement phase, using Transactional Memory (TM). Transactional Memory is an optimistic parallel programming model which attempts to provide fine-grain locking performance while maintaining the ease of programming of coarse-grain locking. Using a software based TM system, we were able to produce a prototype parallel version of the placement phase in the Versatile Place and Route (VPR) software within a short period of time. This implementation required very few modifications to the underlying sequential algorithm. Early results with this prototype on commodity hardware suggest that there is potential for scalable placement performance.

I am currently a Master's student in the Computer Science department at the University of Toronto under supervision of Angela Demke-Brown (CS) and Greg Steffan (ECE).

Despite the popularity and success of neural networks in research, the number of commercial or industrial applications have been limited. A primary cause of this is due to the fact that neural networks are usually implemented as software running on general-purpose processors, which are unable to provide the performance and scalability required in non-academic settings. We will present a distributed architecture for Field Programmable Gate Arrays (FPGA) that takes advantage of the inherent parallelism in neural networks. We focus on the Restricted Boltzmann Machine (RBM), a popular type of neural network that is particularly well-suited to hardware designs. The framework is tested on four Xilinx Virtex II-Pro XC2VP70 FPGA running at 100MHz. The resources support a RBM of 256x256 nodes, which results in a computational speed of 1.85 billion connection-updates-per-second and a speed-up of 85-fold over an optimized C program running on a 2.8GHz Intel processor.

Daniel L. Ly is in his first year of the Master of Applied Science in Computer Engineering program at the University of Toronto. He received his Bachelor of Applied Science in Engineering Science - Computer Option at the University of Toronto. His research interests include biologically inspired artificial intelligence and robotics, and his supervisor is Professor Paul Chow.

WiMAX has emerged as one of the most promising next generation wireless communication systems, and multimedia multicast becomes one of the most popular and profitable applications on it. However, the current state-of-the-art multicast scheduling protocols are not especially designed for WiMAX, and under-utilize the scarce wireless spectrum. In our project, we design an efficient multimedia multicast protocol in WiMAX. The salient highlight of our contribution is a multicast framework to fully exploit the benefits provided by channel and user diversity and dynamically enable users to cooperatively help each other in the multicast sessions. Such cooperative communication is supported with the adoption of OFDMA in WiMAX and random network coding techniques. Our protocol is demonstrated and evaluated as optimal and practical, and is able to improve multicast performance significantly. With such design, people will be able to enjoy video service with their iPods by cooperative data sharing.

I am a third-year Ph.D. student of the Computer Engineering Group in the Department of Electrical and Computer Engineering at the University of Toronto, advised by Professors Baochun Li. I received my M.A.S. and B.Eng. both in Tsinghua University, Beijing, China. Currently, my research interest mainly focuses on wireless networks, including WiMAX, WiFi, Cognitive Radio Networks, etc. In particular, I apply a wide variety of theories, e.g., network coding, stochastic processing, and optimization, in analyzing and designing new protocols for wireless networks. My research projects are supported by LG Electronics Inc. I am easy going, self-motivated, and open-minded. With a passion in both academic and industrial research, I once tried to build my own start-up in Beijing, and received top awards in the Business Plan Competitions, sponsored by Microsoft Research Asia and BV Capital. I am enthusiastic on applying my research findings into practical systems.

Opportunistic routing significantly increases unicast throughput in wireless mesh networks by effectively utilizing the wireless broadcast medium. With network coding, opportunistic routing can be implemented in a simple and practical way without resorting to a complicated scheduling protocol. Due to constraints of computational complexity, a protocol utilizing network coding needs to perform segmented network coding, which partitions the data into multiple segments and encode only packets in the same segment. However, existing designs transmit only one segment at any given time while waiting for its acknowledgment, which degrades performance as the size of the network scales up. In this paper, we propose CodeOR, a new protocol that uses network coding in opportunistic routing to improve throughput. By transmitting a window of multiple segments concurrently, it improves the performance of existing work by a factor of two on average (and a factor of four in some cases). CodeOR is especially appropriate for real-time multimedia applications through the use of a small segment size to decrease decoding delay, and is able to further increase network throughput with a smaller packet size and a larger window size.

Yunfeng Lin received his B.Eng. degree in 2000 from the Department of Computer Science and Technology, Tsinghua University, China, and his M.Math. degree in 2005 from the School of Computer Science, University of Waterloo. He is currently a Ph.D. candidate at the Department of Electrical and Computer Engineering, University of Toronto. He has broad interests in computer networking, and his present research focuses on performance evaluation and distributed algorithm design in wireless networks.

Network coding has been leveraged with cooperative diversity to improve performance in single channel wireless networks. However, it is not clear how network coding based cooperative diversity can be exploited effectively in multi-channel networks where overhearing is not readily available. Moreover, the question of how to practically realize the promising gains available, including multi-user diversity, cooperative diversity and network coding in multi-channel networks, also remains unexplored. This work represents the first attempt to unravel these two questions. In this paper, we propose XOR-CD, a novel XOR-assisted cooperative diversity scheme in OFDMA wireless networks. It can greatly improve the relay efficiency by over 100% mostly, thus uplifting the throughput performance by over 30% compared to conventional cooperative diversity scheme. In addition, we formulate a unifying optimization framework that jointly considers relay assignment, relay strategy selection, channel assignment and power allocation to reap different forms of gains. We design efficient polynomial time algorithms to solve the NP-hard problem with provably the best approximation factor, and verify their effectiveness using realistic simulations.

Hong is a 2nd year M.A.Sc candidate in Computer group. His research interests focus on the general area of wireless networking and communications. Specifically, he is interested in dynamic spectrum access, including spectrum trading and auctions. His work has been published in top conferences including IEEE INFOCOM 2009. Hong did his undergraduate work in Department of Information Engineering, The Chinese University of Hong Kong, Hong Kong, and was awarded the B.Engr. degree with first class honour, and a minor in Business Administration in 2007. In his undergraduate years, Hong achieved excellent academic performance both departmental-wide and university-wide. He was consistently placed on the Dean’s List of Faculty of Engineering and New Asia College from 2004 to 2007. His undergraduate thesis focuses on the performance of network coding in wireless peer-to-peer networks, under supervision of Professor Robert Li. Besides course work, he has also worked as a committee member of mainland undergraduate association, and did a summer internship at HP Singapore.

Matrix Multiplication is used in many signal processing applications, however suffers from repetitive memory latency and intense computation. Scalable Macro-Pipelined Accelerator (SMPA) for Matrix Multiplication is a proposed Architecture for Matrix Multiplication that tackles the obstacles found in current implementation of Matrix Multiplication with accelerators and the short comings from the nature of the implementation with general purpose computers.

Vincent Mirian is M.A.Sc student supervised by Paul Chow. His research is related to threading on FPGAs. Vincent Mirian completed his undergrad at York University in Computer Engineering.

The Compute Unified Device Architecture (CUDA) has become a de facto standard for programming NVIDIA GPUs. However, CUDA places on the programmer the burden of packaging GPU code in separate functions, of explicitly managing data in GPU memories, and of manually optimizing the utilization of GPU memories. Practical experience shows that the programmer needs to make significant code changes, often tedious and error-prone, before obtaining an optimized program. We have designed, hiCUDA, a high-level directive-based language, that allows programmers to perform these CUDA tasks in a simpler manner, and directly to the sequential code. We have prototyped a source-to-source compiler that translates a hiCUDA program to an equivalent CUDA program, and used five standard CUDA benchmarks to show that the simplicity hiCUDA provides comes at no expense to performance. Currently, we are finalizing a release of the compiler, after which we will do a formal usability study of the language.

David Han is a M.A.Sc. candidate in Computer Engineering at the University of Toronto, working under the supervision of Prof. Tarek Abdelrahman. He received his B.A.Sc. degree in Computer Engineering from the University of Toronto in 2007.

Debugger is a vital tool to maintain/improve programmer’s productivity. Existing debuggers provide rich set of functionalities to assist program debugging, but generally lack the ability of program checkpointing and resume execution from failed attempts without restarting execution from the beginning. Checkpointing is a process to take program snapshots and enable execution to rewind safely and thoroughly to the precisely checkpointed states, recovering from program failures. In the past few years, we have developed an efficient software-only checkpointing compiler optimization framework. It contains base checkpointing passes and a large number of optimization transformations. The base checkpointing passes activate user-annotated programs with software-only checkpointing support, while the aggressive compiler transformations aim to reduce software checkpointing overhead to its minimal. In this work, we propose a software solution that leverages on our existing checkpointing framework to provide checkpointing support for a debugger. Users only need to mark regions of interest in the source code. Our compiler framework will take over the details, including activating checkpointing region and performing program analysis and optimizations. Upon a failure in the checkpointed region, the user can simply issue a checkpoint-abort command, which overwrites the potential problem and safely rewinds execution back to the beginning of the checkpointed region.

Chuck (Chengyan) Zhao is a Ph.D. candidate in the department of Computer Science at the University of Toronto. His research interests include compilers, computer architectures, runtime systems and all aspects of parallelism. Starting Sept. 2007, he is an IBM CAS Ph.D. fellow working closely with the IBM Toronto Lab compiler development. His current focus is on developing compiler techniques to automatically parallelize general-purpose programs for multi-core (CMP) architectures.

Navid is a fourth-year PhD student at the University of Toronto working with professor Zaky. His PhD research focuses on using asynchronous design techniques to build low-power, high-performance, and reliable digital systems both synchronous and asynchronous.

We propose a cognitive channel reuse framework for autonomous femtocell deployment in a wireless cellular system. The objective is to manage the co-channel interference caused by user-deployed femtocells to the public network users. Instead of fully reusing 100% of the macrocellular channels, partial reuse is cognitively determined in femtocells based on their individual channel environment. Simulation shows very optimistic SINR performance in comparison to the approach without cognitive channel reuse. We claim that the proposed framework offers a 4G view on spectrum management in an autonomous cellular architecture.

Yang-Yang Li is a 4th year Ph.D. student working with Professor Elvino Sousa. His current research is about Autonomous Interference Management for 4G Cellular Networks. He has spent three months in Tokyo, Japan as an associate researcher at Waseda University where he mainly focused on Femtocell Management in CDMA-based Cellular Systems.

Efficient resource management and Quality of Servise (QoS) provisioning are the most important concerns in cellular networks. Transmit power control constitutes one of the main areas in resource allocation which was originally proposed to tackle the near-far problem. This technique has taken a more general form to support the active users with their required SINRs, which is referred to as SINR-balancing. In this work the combined SINR-balancing power and rate control will be studied with a focus on scheduling and base station assignment which will be formulated independently for the uplink and downlink scenarios in an autonomous infrastructure-based cellular network where the access points are randomly deployed. The terminal limitations such as maximum transmit power level and their capability to support only a limited number of data rates will be taken into consideration. In multi-carrier systems, terminals whose position/power levels impose excessive interference on the performance of the rest of the network can be permanently removed and accommodated on other carriers. This leads to the joint base station and carrier selection optimization problem which will be addressed herein.

Bijan Golkar was born in Tehran, Iran. He received the B.S. degree in electrical engineering from K.N.Toosi University of Technology, Tehran, Iran, in 2005 and the M.A.Sc degree in electrical engineering from Carleton University, Ottawa, Canada in 2007. He is currently working toward the Ph.D. degree at University of Toronto. His current research interests include transmitter power control and multi-QoS radio resource management in Autonomous Infrastructure-based cellular networks.

Improving logic density and maximum clock rates of FPGAs have led to an increasing number of FPGA-based system-on-chip designs, which in turn increasingly contain one or more soft processors---processors composed of programmable logic on the FPGA. Despite the raw performance drawbacks, a soft processor has several advantages compared to creating custom logic in a hardware-description language: it is easier to program (e.g., using C), portable to different FPGAs, flexible (i.e., can be customized), and can be used to communicate with other components/accelerators in the design. We are therefore motivated to better understand the architectural trade-offs and improve the efficiency of these systems. For real workloads (e.g. packet processing applications), a designer can choose to decompose his application in a number of threads to exploit the benefits of parallelism. Given those threads that synchronize and share data structures, our focus is on studying processor architectures (along with compiler techniques) that exploit most efficiently the FPGA resources to provide the best throughput.

Martin Labrecque is a Ph.D. student in the Computer engineering group at the University of Toronto. He completed his Master's at the University of Toronto and his B. Eng. at Ecole Polytechnique of Montreal. His research interests include network processing, co-design, reconfigurable architectures and artificial intelligence.

Using FPGAs to accelerate the Analytical model of CDO Pricing

Dharmendra Gupta is a MASc Student, working under the supervision of Professor Paul Chow. He finished his Bachelors from University of Toronto, in 2007.

Given an algorithm, our goal is to find the computing architecture that will provide the best performance. Our approach can be split into two main phases: First-order and higher-order matching. In the first-order phase, we will seek those characteristics of algorithms that contribute the most to performance. We believe the memory access patterns of algorithms are the key issue because the memory is the major bottleneck in computing systems. We will build architectural models to capture the major characteristics of architectures based on the memory system architecture. In the higher-order phase, other characteristics of algorithms are considered to refine the results. Algorithms will be analyzed using dataflow graphs. The dataflow graphs reveal the maximum possible parallelism within algorithms. Finally, the run times of the dataflow graph executions on the architecture models are measured by simulation. The architecture showing the highest performance will be the best match for the algorithm under study.

Alireza Heidar-Barghi received his B.Sc. in Electrical Engineering from Sharif University of Technology (Tehran, Iran). He received a Master of Applied Science in Electrical and Computer Engineering from Queen's University at Kingston, Ontario. He is currently doing his Ph.D. under Professor Paul Chow's supervision in Computer Engineering at the University of Toronto. His research interests include high-performance computer architectures, FPGA applications, and digital signal processing.

Recent national energy policies around the world are aiming to have 20% of electricity production from renewable energy. Offshore wind farms are expected to play a major role to meet this target. The interconnection of these units represents a technical challenge because of the stochastic nature of the production, and the location of, units. The electricity produced in existing offshore wind farms goes through many conversion stages from dc to ac and back again. The objective of the research is to develop a new method for interconnecting wind turbines based on a dc collector network. By doing so, the number of intermediate converters is reduced and it could increase the efficiency. The motivation for this research is to propose an efficient and cost effective way to interconnect wind turbines that can be implemented in future wind farms.

Etienne Veilleux received the B. Eng. (Honours) degree in electrical engineering from McGill University, Montréal, QC, Canada, in 2007, and is now pursuing the M.A.Sc degree with the Department of Electrical & Computer Engineering at the University of Toronto, Toronto, ON, Canada. His research interests include integration of wind farms and power electronics.

Field-Programmable Gate Arrays (FPGAs) are digital logic devices whose functionality can be reprogrammed after fabrication. Unfortunately, there is overhead from reprogrammability and this results in higher cost and delay for FPGAs compared to fixed functionality devices. To architect a flexible, low cost, and high speed FPGA, it is important for the architect of the FPGA to determine what to make programmable and what to make fixed. To perform this task, an architect typically employs an empirical experiment to evaluate and compare the effectiveness of different FPGA architectures. Packing is an important step in this empirical flow and my work-in-progress is to create a generic packer for FPGAs that contain different types of programmable and fixed components.

Jason Luu is currently a MASc student studying under Prof Jonathan Rose and Prof Jason Anderson. He received his BASc from the University of Waterloo in 2007. His primary interest is in architecture and computer-aided design (CAD) for FPGAs.

Debugging design errors is a challenging manual task which requires the analysis of long simulation traces. Since these error traces can easily exceed hundreds of clock cycles, trace compaction techniques help engineers analyze the cause of the problem by generating a new error trace with fewer clock cycles. In this talk will present an optimal trace compaction technique based on incremental SAT. The approach builds a SAT instance from the Iterative Logic Array representation of the circuit and performs a binary search to find the minimum trace length. Circuit properties are preserved in the compacted trace by encoding them as constraints into the SAT problem.

Yibin Chen received the B.A.Sc. degree in computer engineering from the University of Waterloo, Waterloo, ON. He is currently working toward the M.A.Sc. degree in computer engineering at the University of Toronto. His research interests include formal methods for verification, design debugging, and satisfiability solvers.

In large-scale P2P live streaming systems, it is shown that peers in an unpopular channel often experience worse streaming quality than those in popular channels. By analyzing 130 GB worth of traces from a large-scale P2P streaming system, UUSee, we observe that a large number of "unpopular" channels, those with dozens or hundreds of concurrent peers, tend to experience inferior streaming quality. We also notice a short lifespan in these channels, which further exacerbates streaming quality. To derive useful insights towards improving streaming performance, we seek to thoroughly characterize important factors that may cause peer volatility in unpopular channels. Specifically, we conduct a comprehensive statistical analysis on the impact of various factors on peer lifespan, using survival analysis techniques. We found that the initial buffering level, the variance of peer indegree, and the peer joining time all have important effects on the lifespan of peers.

Zimu Liu is currently a second-year Master’s student of the Computer Engineering Group, in The Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. He received my B.E. degree in Information Security from Nanjing University of Posts and Telecommunications, Nanjing, China. His research interests focus on statistical study on the large-scale peer-to-peer applications and design of algorithms for distributed systems. In particular, he is interested in deriving insights from extensive measurements and statistical studies of real-world commercial live streaming applications, and improving performance and quality of peer-to-peer video-on-demand systems.

Systems can become misconfigured for a variety of reasons such as operator error or buggy patches. When a misconfiguration is discovered, usually the first order of business is to restore availability, often by undoing the misconfiguration. To simplify this task, we propose Ocasta, which uses a statistical analysis of how the contents of a file changes over time to automatically identify which files contain configuration state. In this way, Ocasta reduces the number of files a user must manually examine during recovery, as well as allowing versioning file systems to make more efficient use of their versioning storage. The two key insights that enable Ocasta to identify configuration files are that configuration state must persist across executions of an application and that configuration state changes at a slower rate than other types of application state. Ocasta applies these insights through a set of filters, which eliminate non-persistent files from consideration and a novel similarity metric, which measures how similar a file’s versions are to each other. Together, these two mechanisms enable Ocasta to identify all 72 configuration files out of 2366 versioned files from 6 common applications in two user traces, while mistaking only 33 non-configuration files as configuration files. Ocasta allows a versioning file system to eliminate roughly 85% of non-configuration file versions from its logs, thus reducing the number of files versions that a user must try to recover from a misconfiguration.

James Huang is a M.A.Sc candidate expecting to graduate in Aug, 2009.

A parallel arrangement of voltage-sourced converters making use of independent controllers is proposed as a more modular and redundant motor drive. In this configuration, two or more inverters with independent controllers use common dc- and ac-buses to feed a single permanent-magnet synchronous motor. This arrangement is potentially more cost-effective and reliable than a traditional motor drive, but necessitates additional control to ensure load sharing and to minimize circulating currents. 0-sequence and drooped-speed controllers have been developed as extensions to standard field-oriented control, and the performance during speed steps has been evaluated in simulation and in an experimental setup.

D. Fingas was born in Cobourg, Ontario. After completing his undergraduate degree in Engineering Science (Electrical Option) at the University of Toronto, he worked at an engineering consulting company for a year in power engineering. Having returned to U of T, he is now in the second year of an M.A.Sc. in the Energy Systems Group. His research interests include motor drives and control and application of economically-sensible renewable generation.

The presentation on the Connection conference will present a simple and very practical implementation of the concept of capacitor charge balance in mixed-signal continuous-time peak current program mode (CPM) controllers to achieve fast transient responses for low-power switch mode power supplies (SMPS). The controller has three modes of operation where in steady-state it operates as a conventional mixed-signal CPM controller. During transients, the controller switches to its nonlinear mode to achieve very fast transient responses. The third mode consists in a novel and simple implementation of the pulse frequency modulation (PFM) for operation under light loads. The functionality of the proposed controlling techniques was verified experimentally on a 5.5V-to-1.8V, 10W buck converter operating at 1MHz.

Jurgen Aliço was born in Tirana, Albania in 1983. He received his B.A.Sc. degree in Electrical Engineering from the University of Toronto, Toronto, ON in 2007. He is currently pursuing the M.A.Sc degree from the University of Toronto, Toronto, ON. He is also a Research Assistant in the Laboratory of Low-Power Management and Integrated Switch-Mode Power Supplies, University of Toronto. His research interest include digital and mixed-signal controlling techniques for low-power SMPS, power electronics and mixed-signal IC design.

This paper introduces a solution of the dynamic economic dispatch (DED) problem using a hybrid approach of Hopfield neural network (HNN) and quadratic programming (QP). The hybrid algorithm is based on using enhanced HNN; to solve the static part of the problem; and the QP algorithm for solving the dynamic part of the DED. This technique guarantees the global optimality of the solution due to its look-ahead capability. The new algorithm is applied and tested to an example from the literature and the solution is then compared with that obtained by some other techniques to prove the superiority and effectiveness of the proposed algorithm.

Mohamed Kamh was born in Cairo, Egypt in 1980. He earned both his B.Sc and M.Sc. degrees in electrical engineering at University of Ain Shams, Cairo, Egypt at 2003 and 2007 respectively. He is currently with the Energy Systems Group-ECE department, UofT since January 2008 where he is pursuing his PhD degree. His research interests are power system planning and operation, integration of distributed energy resources into power systems, and developing software tools for analysis and planning of deregulated power systems.

Evaluating the effectiveness of a new physical- or architectural-level optimization requires a new or a modified physical-level implementation. This thesis studies three components of modern dynamically-scheduled superscalar processors; for these components, neither through physical-level investigations nor models have been reported: Counting Bloom Filters (CBFs), Checkpointed Register Alias Tables (RATs) and Compacted Matrix Schedulers (CMSs). Hardware CBFs help improve the energy and speed of membership tests by maintaining an imprecise and compact representation of a large set to be searched. We study the energy and latency of CBF implementations using full custom layouts in a commercial 0.13 µm fabrication technology. One implementation, S-CBF, uses an SRAM array of counts and a shared up/down counter. Our novel implementation, L-CBF, utilizes an array of up/down linear feedback shift registers (LFSRs) and local zero detectors. Circuit simulations show that for a 1K-entry CBF with a 15-bit count per entry, L-CBF compared to S-CBF is 3.7x or 1.6x faster and requires 2.3x or 1.4x less energy depending on the operation. We also present analytical energy and delay models for L-CBF. These models can be useful in the early stages of architectural exploration where actual physical implementations are unavailable or hard to develop due to the time and/or cost constraints. The model estimations are within 5% and 10% of Spectre™ simulation results for latency and energy respectively. This range of accuracy is acceptable for architectural-level studies. This work studies latency and energy variation trends of the RAT as a function of the number of global checkpoints (GCs), issue width and window size. Our work improves upon previous RAT checkpointing work that ignored the actual latency and energy tradeoffs and focused solely on evaluating performance in terms of instructions per cycle (IPC). Measurements are based on full-custom checkpointed RAT implementations developed in a commercial 0.13 µm fabrication technology. Using physical- and architectural-level evaluations together, this work demonstrates the tradeoffs among the aggressiveness of the RAT checkpointing, performance and energy. Our work shows that, as expected, focusing on IPC alone incorrectly predicts performance. Our results justify checkpointing techniques that use very few GCs (e.g., four). This work also presents analytical latency and energy models for SRAM-based RAT. The model estimations are within 6.4% and 11.6% of circuit simulation results respectively. This work also determines and compares the latency and energy variation trends of the checkpointed SRAM-based RAT (sRAT) and checkpointed CAM-based RAT (cRAT) as a function of the window size, the issue width and the number of global checkpoints (GCs). Compared to sRAT, cRAT is more sensitive to the number of physical registers and issue width, however less sensitive to the number of GCs. We have found that when the number of GCs passes a limit, cRAT becomes faster than its equivalent sRAT. For instance, with 64 architectural registers and 128 physical registers, having more than 20 GCs makes a 6-bit, 128-entry cRAT faster than its equivalent 7-bit, 64-entry sRAT. In most cases, cRAT is less energy efficient that sRAT, hence this work proposes an energy optimization for the cRAT. This optimization selectively disables cRAT entries that do not result in a match during lookup. The energy savings are, for the most part, a function of the number of physical registers. For instance, for a cRAT with 128 entries energy is reduced by 40%. Previous work focused on the architecture of CMS and argued in support of its speed and scalability advantages. However, neither actual physical-level investigations nor analytical models have been reported for this compacted scheduler. Using full-custom layouts in a commercial 90 nm fabrication technology, this work investigates the latency and energy variations of the matrix and its accompanying logic as a function of the issue width, the window size and the number of GCs. We also propose an energy optimization that reduces the energy by 10% or 18% depending on the scheduler size.

Elham Safi (S’05) received the B.Sc. and M.Sc. degrees respectively in computer hardware engineering and computer architecture from the University of Tehran, Iran. She is currently pursuing her Ph.D. degree in the Department of Electrical and Computer Engineering, University of Toronto. Her research interests include computer architecture with emphasis on hardware design and implementation.

Studying the behaviours of large-scale networks such as the Internet is challenging due to the immense size of the problem. Simulation techniques are often employed to understand the complex interactions between various network components before new applications or protocols can be deployed. The three most prevalent techniques used in networking research today are software simulation, emulation using clusters of CPUs and experimentation using large-scale testbeds. Each offers a different trade-off between accuracy of result, speed of experiments, and cost. We propose an FPGA-based packet network simulator that is cheap, fast and accurate. Our network simulator-on-chip leverages the parallelism that exists in the events modeled when simulating a network. We present a hardware architecture that can model an arbitrary packet network composed of traffic sources, sinks, routers and network links with configurable latency and bandwidth. Preliminary results show a 100x speedup over software simulation. This work is a project for ECE1373, taught by Prof. Paul Chow.

Henry Wong is a first-year Ph.D. student in the Department of Electrical and Computer Engineering at the University of Toronto, under the supervision of Prof. Jonathan Rose. His current research interests are in soft-processor systems. He received an M.A.Sc. degree from the University of British Columbia in 2008, on GPU-CPU heterogeneous systems. Prior to that, he received a B.A.Sc. degree in Computer Engineering from the University of Toronto in 2006. Danyao Wang is a first-year M.A.Sc. student in the Department of Electrical and Computer Engineering at the University of Toronto, under the supervision of Prof. Greg Steffan. Her current project is on FPGA-acceleration of interconnection network simulation. She received a B.A.Sc. degree in Engineering Science (Electrical Option) from the University of Toronto in 2008.

In radiation therapy, a treatment plan is designed to make the delivery of radiation to a target more accurate, effective and less damaging to surrounding healthy tissues. However, respiratory motion creates great difficulty in treatment due to correlated tumor motion. Unexpected changes due to coughs and sneezes are not taken into account and no measures are taken to make the treatment plan adapt to changes. An accelerometer device was built to be used in conjunction with an infrared camera to provide measurements of a patient's respiratory motion. We will look at the physiology of a cough to gain insight on what useful information we can draw from these sensor measurements. This knowledge is then used to generate a set of features for each respiratory cycle to train a classifier using Bayesian discriminant functions. Finally we will look at using an ARMA model for the forecast of these events.

I finished my undergraduate studies here at U of T in the ECE department. I'm co supervised by Prof. Raymond Kwong from the System Control group and Hamideh Alasti from the department of Radiation Physics at Princess Margaret Hospital.

A discrete event system (DES) diagnoser is an agent that estimates a DES plant's runtime states, in order to detect and identify possible runtime faults in the plant. The diagnoser can be realized with software, but this would require microprocessors or microcontrollers, which are unsuitable in some applications. We have developed a hardware realization that implements the diagnoser as an interconnected array of simple digital circuits. Control signals generation and diagnosis computation can also be implemented with circuits. The size of the diagnoser circuit scales linearly with the number of plant states. Desirable "glitch-free" property of the circuit is established through a detailed analysis of the diagnosis algorithm. As a proof of concept, the circuit design was simulated, constructed and tested on a simple plant.

Samuel Tien-Chieh Huang graduated from Engineering Science at University of Toronto in 2004. He is currently a Ph.D. candidate jointly supervised by Prof. Davison and Prof. Kwong in the Systems Control Group at U of T, where he also completed his M.A.Sc. degree in 2007. His current research interest includes theory and application of fault-tolerant controls. Samuel is also an avid programmer, and has held internship positions in Altera and Google.

A convoy problem is formulated and solved for two four-wheeled vehicles. The task is for the second vehicle to follow the leader's trajectory with a constant time delay. This delayed trajectory can be viewed as the trajectory of a delayed leader. The novel constant-time-delay concept allows for the estimation of the delayed leader's speed and heading using the vehicle kinematics. Decoupled longitudinal and lateral controllers are developed based on the constant-time-delay approach. The lateral controller includes a look-ahead feature to compensate for steering delays. Successful field trials were conducted with full-sized military vehicles on a 1.3-kilometre test track. The tracking errors from differential global positioning system (DGPS) ground truth covering 13 kilometres are presented. A video of a field trial along with ground truth inlay will also be presented.

Hien K. Goi is an MASc student in the Systems Control Group and is co-supervised by Prof. Tim Barfoot (UTIAS) and Prof. Bruce Francis (ECE). His research is on the design and development of a control system for autonomous vehicles in a vehicle convoy. Hien obtained his BASc in Computer Engineering from the University of Waterloo.

In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to the difficulty of the problem by exponentially increasing the statespace of the design. In this work, a novel memory model for design debugging is presented. It models memory succinctly by avoiding an explicit representation for each memory bit. The method uses the simulation of the erroneous design to guide the debugging process. This results in a parameterizable formal encoding that grows linearly with the erroneous trace length, significantly reducing the memory requirements of the debugging problem.

There has been recent interest in both the theory and the realization of superluminal and negative group velocities. It has been shown that superluminal and negative group velocities do not lead to superluminal information transfer. This is a good thing since the latter would violate Einstein causality. Knowing that superluminal information transfer remains impossible, we would like to explore the practical usefulness of superluminal and negative group velocities from a detection theoretic point of view. For my master’s thesis, I have only considered spatially negligible electronic circuits for which we can only talk of group delays rather than group velocities. However, a similar analysis can be applied to spatially extended systems where group velocities are meaningful. In essence, time-varying error probability borrowed from detection theory can give a good indication of the practical detection latency of a negative group delay circuit as compared to that of a conventional circuit.

Levent Kayili received his B.A.Sc. degree in electrical engineering from the University of Waterloo in 2007. Currently, he is an M.A.Sc. candidate in the electromagnetics group. His research interests include the detection theoretic analysis of superluminal and negative group delays for microelectronic circuits.

Epilepsy is a dynamical neurological disorder that afflicts 0.6-1% of the population. The majority of epilepsy cases can be successfully treated either pharmacologically or surgically while the remaining cases are referred to as intractable epilepsies and are the target of our work. Our research focuses on the use of electrical stimulation to inhibit the onset of seizures using a feedback control system. The controller employs an error signal which is derived from an interictal reference generator and live data acquired from the in-vitro rat hippocampal slice. The reference generation algorithms used includes a logistic map, and a radial basis function model. The error signal generated is fed into a bank of modes and is subsequently used to drive a stimulation electrode in the slice with the goal of maintaining healthy brain activity. This work is very promising in light of the recent high profile successes in deep brain stimulation (DBS). We hope that our biologically inspired stimulation and control paradigm can be applied to DBS to increase efficacy.

Sinisa Colic - 2nd year M.A.Sc student in the ECE Biomedical department. Research focused on prediction and control of seizures. Josh Dian - 2nd year M.A.Sc student in the ECE Biomedical department. Research focused on seizure stimulation control hardware.

Femtosecond lasers have given access to nonlinear optical interactions that can be utilized to alter materials in new ways. For optically transparent media, such interactions have opened new possibilities in fabricating three-dimensional micro- and nano-scale structures and for creating refractive index modifications in materials. This talk will survey our group’s capabilities in capturing these nonlinear optical interactions to develop laser processes for producing waveguides, couplers, photonic crystals and microfluidic channels. We then present laser-write approaches for the three-dimensional integration of these optical and microfluidic devices in glass as a new direction for analyte separation and detection and optofluidic sensing, on a lab-on-a-chip platform. While the fundamentals of the laser-material interaction mechanisms will be briefly overviewed, the main focus will be on the novel devices and applications that they make possible.

Jason Grenier received the Bachelor’s and Master’s of Applied Science degrees in Electrical Engineering from the University of Waterloo in 2003 and 2006, respectively. During this time, Jason acquired two years of industry work experience including internships at Cypress Semiconductor, Nortel Networks, and Photonics Research Ontario. Jason is currently a Ph.D. candidate in the Photonics Group in the Department of Electrical and Computer Engineering at the University of Toronto. His present research interest is using femtosecond laser technology to control and harvest laser interactions to expand the frontiers of three-dimensional micro and nanofabrication for novel lab-on-a-chip application. Jason is presently an NSERC post-graduate scholarship holder and has recently won awards from the Canadian Institute for Photonics Innovation and the Ontario Centres of Excellence. He is a member of the IEEE, SPIE, OSA, and the Institute for Optical Sciences. Web: http://photonics.light.utoronto.ca/laserphotonics/index.html