In this paper, we have presented a family of centralized field-configurable memory architectures. Each architecture is composed of a number of arrays, and a data and address mapping network. The architectures are flexible enough that they can implement logical configurations containing several logical memories of different depths and widths.
An important contribution of this work is the method used to analyze the architectures. We believe that by generating a large number of test configurations stochastically, we can obtain results that are much more useful than those that could be obtained using a handful of ``real'' circuits.
Although this paper has concentrated on centralized architectures, we believe that the evaluation method we have proposed is also useful when comparing distributed architectures. When investigating distributed architectures, however, it is necessary to take into account routing beyond the memory ``boundaries'' and also to consider logic block and memory array placement. Clearly, this is an exciting area of future research.
Figure 7: Effects of changing minimum output width of L1 Data Mapping Block on delay and area
Figure 8: Effects of changing minimum output width of L1 Data Mapping Block on flexibility