Hardware Reference

Processor datapath

Program Counters

The MIPS processor architecture has a feature known as "branch delay slots," which are intended to help the pipeline deal with branch misprediction. Unfortunately, this is less than useless for a non-pipelined processor like the supersmall. To address this issue, another register was added: all processing takes place on the NPC (Next Program Counter) register, while the current instruction is always drawn from the PC (Program Counter) register. This way, branch delay slots are taken care of with a minimum of logic, albeit at the cost of 32 flip-flops.

To contain the exception return address, the EPC (Exception Program Counter) register is implemented exactly the same way, just a step behind the PC register.


The supersmall follows a Harvard Architecture, which means that instruction and data memories are separated, and currently, the instruction memory is read-only. Both are by default 64 KiB (kibibytes), although there is no actual requirement on this size, and their sizes can be reduced or expanded as required. To change the memory sizes, adjust the size of the actual imem.v and dmem.v files in the Quartus Megawizard Plugin Manager, and then adjust the address lines accordingly in system.v. For more details about how to modify the supersmall hardware, see the hardware modification guide.

Although the instruction memory is configured as a straight ROM, the data memory is byte-enabled and dual-port, a system that is used to implement byte, halfword, and full-word operation with a minimum of logic.

The register file is implemented (rather inefficiently: this might change in the future) as two separate but coherent memories that feed into either temporary register A or B. By having two memories, two registers can be read at once, allowing tthe processor to use simpler logic to deal with the MIPS architecture's three-operand instructions.

Temporary Registers

A and B are the temporary shift registers that end up doing most of the heavy lifting, including feeding the 1-bit ALU.


The BRU (Branch Resolve Unit) is a separate module used to compare the values of the two registers referenced in a branch instruction.


The 1-bit ALU, fed by the two temporary registers, performs operations as specified by the state machine.

Coprocessor 0

Although not truly a coprocessor, the MIPS Coprocessor 0 stores several system control registers, four of which are implemented on the supersmall.