State Machine Reference

State	Activities	Next States	Cycles	Exceptions
START-0	Load instruction	START_1	2	None
	Reset branch conditions
START-1	Check branch conditions	START_2	33	Int
	A = rs (decoded)			Bp
	B = rt (decoded)			Syscall
	PC = nPC			RI
	nPC = nPC (branch) or PC+4			CpU
START-2	Choose whether to shift in zeros or data	ALU_0	1	None
	Choose FSM path based on instruction	ALUI_0
		AHIFTL_0
		SHIFtr_0
		BRANCH_0
		LOADSTORE_0
		JUMP_0
		COP0_0
ALU_0	A = rs <op> rt	WRITEBACK_0	33	Ov
ALUI_0	A = rs <op> IMM || rs = IMM (LUI)	WRITEBACK_0	33	Ov
SHIFTL_0	A = rs (shifted)	WRITEBACK_0	33	None
SHIFtr_0	A = rt	SHIFtr_1	33	None
SHIFtr_1	A = A (shifted)	WRITEBACK_0	Variable	None
LOADSTORE_0	A = rt + IMM(SE)	LOADSTORE_1	33	AdEL
		LOADSTORE_2		AdES
LOADSTORE_1	Shift B into upper half	LOADSTORE_2	17	None
LOADSTORE_2	Set byte enable based on instruction	START_0	1	None
	Set write enable based on instruction	WRITEBACK_0
	Either store or load the data in parallel
BRANCH_0	Set branch delay stack	START_0	33	None
	nPC = PC + IMM or PC+4
JUMP_0	nPC = A || nPC = IMM	WRITEBACK_0	33	AdEL
	A = nPC	START_0
COP0_0	A = cop0out || cop0in = B	WRITEBACK_0	33	None
		START_0
WRITEBACK_0	Register = A	START_0	1	None