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For latest information about EDK releases, visit http://www.xilinx.com/edk.
EDK Tools
Wizards for designing systems
- Base System Build Wizard for creating new hardware systems.
- Import Peripheral Wizard to aid the users in adding already existing
cores into a EDK project.
Xilinx Platform Studio Improvement
- User Comments in M*S files are now preserved by the tools.
- Improved synchronization between the different views of Xilinx
Platform Studio.
- Improved graphical interface.
- Most of the EDK 3.2 projects will be automatically updated to the
current version, when opened through XPS in EDK 6.1.
Improved EDK/ISE Integration
- An
XPS source can now be added into ISE Project Navigator as a supported
source type.
Software
Simulator Support for PowerPC
- An
instruction set simulator supporting the PowerPC is available in the
current release.
Simulation
Improvements
- The EDK simulation environment has been enhanced to support multiple
simulation environments. In the latest version of the EDK, users can
now maintain separate behavioral, structural and timing simulation
environments adding to the flexibility of the tool offering.
- Users can now simulate their own cores and top level designs
in Verilog using a mixed language simulator from MTI. Xilinx Processor
IP is simulated in VHDL while the rest of the design can simulated in
Verilog.
- Mixed
Language Simulation is now supported through EDK.
- A
new tool, compedklib introduced for compiling behavioral
simulation libraries. This replaces vmap_edk_libs.
Xilinx
Micro Kernel
- Debugging
of XMK applications is now supported.
- Support
for multiple XMK processes in a single executable.
For more details on EDK tools, refer to Embedded
Software Tools Guide.
Processor IP
User Core Templates and Reference Systems
Source code for processor IP
- As a part of EDK 61 release, source code for all Processor IP, excluding
pay cores, is provided.
Active Processor IP included in EDK 6.1
The following IPs are included in the current release of EDK 6.1 :
- bram_block_v1_00_a
- dcm_module_v1_00_a (New)
- dcr_intc_v1_00_b
- dcr_v29_v1_00_a
- dsbram_if_cntlr_v1_00_a
- dsbram_if_cntlr_v2_00_a (New)
- dsocm_v10_v1_00_a (New)
- fit_timer_v1_00_a
- fsl_v20_v1_00_b
- isbram_if_cntlr_v1_00_a
- isbram_if_cntlr_v2_00_a (New)
- isocm_v10_v1_00_a
- jtagppc_cntlr_v1_00_a
- jtagppc_cntlr_v1_00_b (New)
- lmb_bram_if_cntlr_v1_00_b
- lmb_v10_v1_00_a
- microblaze_v2_00_a
- mii_to_rmii_v1_00_a
- opb2dcr_bridge_v1_00_a
- opb2plb_bridge_v1_00_c
- opb_atmc_v2_00_a
- opb_bram_if_cntlr_v1_00_a
- opb_bram_if_cntlr_v2_00_a
- opb_central_dma_v1_00_a (New)
- opb_ddr_v1_00_b
- opb_emc_v1_10_a
- opb_emc_v1_10_b
- opb_ethernet_v1_00_m (New)
- opb_ethernetlite_v1_00_a
- opb_gpio_v1_00_a
- opb_gpio_v2_00_a (New)
- opb_hdlc_v1_00_b (New)
- opb_iic_v1_01_a
- opb_intc_v1_00_b
- opb_intc_v1_00_c
- opb_jtag_uart_v1_00_b
- opb_mdm_v1_00_b
- opb_mdm_v1_00_c
- opb_memcon_v1_00_a
- opb_opb_lite_v1_00_a
- opb_pci_v1_00_b
- opb_sdram_v1_00_c
- opb_spi_v1_00_b
- opb_sysace_v1_00_a
- opb_timebase_wdt_v1_00_a
- opb_timer_v1_00_b
- opb_uart16550_v1_00_c
- opb_uartlite_v1_00_b
- opb_v20_v1_10_b
- plb2opb_bridge_v1_00_b
- plb_atmc_v1_00_a
- plb_bram_if_cntlr_v1_00_a
- plb_ddr_v1_00_b
- plb_ddr_v1_00_c
- plb_emc_v1_10_b
- plb_ethernet_v1_00_a (New)
- plb_gemac_v1_00_b (New)
- plb_rapidio_lvds_v1_00_a
- plb_sdram_v1_00_c
- plb_uart16550_v1_00_c
- plb_v34_v1_01_a
- ppc405_v1_00_a
- ppc405_v2_00_a (New)
- proc_sys_reset_v1_00_a
- util_bus_split_v1_00_a (New)
- util_flipflop_v1_00_a (New)
- util_reduced_logic_v1_00_a (New)
- util_vector_logic_v1_00_a (New)
Deprecated Processor IP
The following Processor IPs have been deprecated in EDK 6.1 release and
will be removed from the installation in subsequent releases. Note that a
later version of the IP might exist for all the IPs listed below :
- dcr_intc_v1_00_a
- microblaze_v1_00_c
- microblaze_v1_00_d
- microblaze_v1_00_e
- opb2plb_bridge_v1_00_a
- opb2plb_bridge_v1_00_b
- opb_arbiter_v1_02_c
- opb_atmc_v1_00_b
- opb_emc_v1_00_d
- opb_emc_v1_10_a
- opb_ethernet_v1_00_j
- opb_ethernet_v1_00_k
- opb_ethernet_v1_00_l
- opb_intc_v1_00_b
- opb_memcon_v1_00_a
- opb_v20_v1_00_b
- opb_v20_v1_10_a
- opb_zbt_controller_v1_00_a
- plb2opb_bridge_v1_00_a
- plb_emc_v1_00_d
- plb_emc_v1_10_a
- plb_gemac_v1_00_a
- plb_uart16550_v1_00_b
The following IPs have been removed from the EDK 6.1 installation :
- lmb_bram_if_cntlr_v1_00_a
- lmb_lmb_bram_if_cntlr_v1_00_a
For more details about Processor IP, refer to Processor
IP Reference Guide.
Restrictions
Simulation
- ModelSim
XE is supported only for MicroBlaze structural and timing simulation
only.
- EDK
6.1 does not support Verilog behavioral simulation models.
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