| Main | Assembly Programming | Input/Output | Memory | Computer Architecture | Advanced Topics |
Every rotation of a motor causes a switch to be pushed. The switch, like most mechanical switches, ‘clatters’ or bounces when the contacts come together, causing an interval when a single press causes multiple closures. This bouncing can continue for just under 3 milliseconds.
The switch is linked into the memory map of a 68000 processor at bit 0 of location $FFFFF000. It is connected so that the bit will read a ‘1’ when the switch is open, and a ‘0’ when closed and not bouncing. The bouncing will cause alternating zeros and ones.
For ease of any analysis you do, assume that every instruction takes 1 usec., regardless of addressing mode.
If the switch were connected to a falling-edge-sensitive interrupt request line what problem could result during the bouncing? And what is one way the problem might be solved?
Problem:
Multiple interrupts, one per bounce
Solutions:
Disable interrupts in ISR during bounce time
Put debounce as in Question 37 in the ISR
Use hardware debounce circuit
Use flag, set flag while bouncing and don’t count
