ECE243 Practice Question Website

Fill in the following table for a processor cache where the processor has a 32 bit word address and the cache has 512 blocks of 16 words.
512 = 2⁹

Mapping Method	Tag Size (bits)	Block (or Set) Address Size (bits)	Word Select Address Size (bits)
Direct
Fully Associative
2-way Set Associative
4-way Set Associative

Assuming you start with an empty 2-way Set Associative cache as above, and that the following addresses are accessed in the order given. Indicate which cache sets and blocks the following addresses come from or replace, the value of the block’s valid bit and whether the address generates a cache miss or a hit. Assume the replacement algorithm is Least-Recently-Used.
For clarity, the four high order zeros in the addresses given are not printed.

Address	Miss or Hit	Cache Set	Block # in Set	Reasoning
$F002
$A202
$B202
$F00C
$E002
$F012
$0002
$F002
$0006
$F006
$FB02

Answer

Mapping Method	Tag Size (bits)	Block (or Set) Address Size (bits)	Word Select Address Size (bits)
Direct	32-13=19	9	4
Fully Associative	32-4=28	0	4
2-way Set Associative	32-12=20	8	4
4-way Set Associative	32-11=21	7	4

Address	Miss or Hit	Cache Set	Block # in Set	Reasoning
$F002	M	00	0	Middle 2 hex digits give set
$A202	M	20	0	New tag
$B202	M	20	1	New tag
$F00C	H	00	0
$E002	M	00	1	New tag
$F012	M	01	0	New tag
$0002	M	00	0	New tag, LRU replacement
$F002	M	00	1	Block was replaced
$0006	H	00	0
$F006	H	00	1
$FB02	M	B0	0	New tag