One method to free up some pins

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Posted by Michael van Dam on March 10, 1998 at 20:20:39:

For those of you who are convinced the lab cannot be done with
the number of pins available on the FPGA board, consider the
following.

Instead of driving all address pins from the FPGA, why not drive
some 'directly' from VCC and GND on the protoboard?

===================
VERY IMPORTANT NOTE:
Do not connect GND and VCC directly into the address
pins, otherwise you will cook the 68000. Instead,
pass them through discrete tri-state inverters which
can be found in one of the chips in your hardware kit.
A pullup resistor (about 5k) is needed at the output
of each inverter.
===================

For example, the address which your circuit drives on the address
lines is always 08XXcc, where 'XX' and 'cc' come from registers
in your circuit. The eight most significant bits "00001000" never
change, and can be hardwired, through a tri-state inverter directly
to the address lines. When your FPGA drives the rest of the
address lines, you will need to assert an output enable signal at
the same time, so that these tri-state buffers will drive the
hardwired value into the upper address bits.

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Comments:
: For those of you who are convinced the lab cannot be done with : the number of pins available on the FPGA board, consider the : following. : Instead of driving all address pins from the FPGA, why not drive : some 'directly' from VCC and GND on the protoboard? : =================== : VERY IMPORTANT NOTE: : Do not connect GND and VCC directly into the address : pins, otherwise you will cook the 68000. Instead, : pass them through discrete tri-state inverters which : can be found in one of the chips in your hardware kit. : A pullup resistor (about 5k) is needed at the output : of each inverter. : =================== : For example, the address which your circuit drives on the address : lines is always 08XXcc, where 'XX' and 'cc' come from registers : in your circuit. The eight most significant bits "00001000" never : change, and can be hardwired, through a tri-state inverter directly : to the address lines. When your FPGA drives the rest of the : address lines, you will need to assert an output enable signal at : the same time, so that these tri-state buffers will drive the : hardwired value into the upper address bits.

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