Posted by Michael van Dam on March 14, 1998 at 13:18:09:
In Reply to: VHDL conditions posted by Jayesh T. Patel on March 13, 1998 at 16:00:52:
: IF (sigA /= '0') THEN
: IF (sigA = '1') THEN
: Or will the first one also be true for high impendance
: on sigA?
: Thanks,
: Jayesh.
Technically, the first one is also true for the high impedance state,
provided that sigA is a STD_LOGIC type. However, the distinction
between the two statements above is useful only for simulation
purposes, and not real circuits.
That is, in a real circuit, you would never want to 'look' at a signal
which does not have a definite '0' or '1' value. If the input is held
in a high-impedance state, then likely it is pulled to high with a
pull-up resistor, in which case it is really a '1'. (If there is no
pull-up, then the circuit interacting with the input will cause it
to be interpretted as either a '0' or a '1' and the output will be in
some indeterminate state, 'X'; the circuit can never conclude that the
input is in the 'Z' state.)