Re: Lab 4 - Loop to measure time

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Posted by Jayesh T. Patel on March 23, 1998 at 16:45:25:

In Reply to: Re: Lab 4 posted by John Chappel on March 22, 1998 at 06:57:32:

: : At the bottom of the page under LAB REQUIREMENTS, our
: : assignment sheet says:
: : "Write a 68000 assembly program to compute the average
: : of the same data block. Compare the speed of the
: : co-processor to the speed of the assembly routine.
: : Which is faster and by how much?"

: : My question is this: HOW?

: : (Last time I checked, my stopwatch only gave a
: : 1 millisecond resolution and it seems a stopwatch with
: : a 100 nanosecond resultion would be more appropriate
: : in this situation :)

: :
: : Thanks,
: : JTP

: Put the whole thing in a big loop.

I'm sorry, I should have been more specific.
For the assembly code, I can see how this is done. No probemo.
My concern is with the FPGA. Suppose we write an assembly language
program that does the following:

1) Set internal counter (data register)
2) Write to FPGA ADDR_REG
3) Write to FPGA CNTL_REG (to tell it to read x values from memory,
average them and write the result to the next memory location)
4) decrement counter
5) loop back to 1 if the counter is still positive

At the end of step 3) who will have control of the bus? Will the 68K definitely
give it up or will it try to finish a few more instructions first?

Thanks for the help,

JTP

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: : : : At the bottom of the page under LAB REQUIREMENTS, our : : : assignment sheet says: : : : "Write a 68000 assembly program to compute the average : : : of the same data block. Compare the speed of the : : : co-processor to the speed of the assembly routine. : : : Which is faster and by how much?" : : : My question is this: HOW? : : : (Last time I checked, my stopwatch only gave a : : : 1 millisecond resolution and it seems a stopwatch with : : : a 100 nanosecond resultion would be more appropriate : : : in this situation :) : : : : : : Thanks, : : : JTP : : Put the whole thing in a big loop. : I'm sorry, I should have been more specific. : For the assembly code, I can see how this is done. No probemo. : My concern is with the FPGA. Suppose we write an assembly language : program that does the following: : 1) Set internal counter (data register) : 2) Write to FPGA ADDR_REG : 3) Write to FPGA CNTL_REG (to tell it to read x values from memory, : average them and write the result to the next memory location) : 4) decrement counter : 5) loop back to 1 if the counter is still positive : At the end of step 3) who will have control of the bus? Will the 68K definitely : give it up or will it try to finish a few more instructions first? : Thanks for the help, : JTP

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