Posted by John Chappel on January 18, 1998 at 13:19:06:
In Reply to: Lab1 Question posted by Jim on January 18, 1998 at 12:17:21:
The differential is derived from the D's as shown on page 1. As you can see,
the differential is really just the same as D+ in this lab.
Figure 1. just shows the clock recovery circuit. The recevier
clock can then be used to drive the rest of your circuit. The
idea is that the active edge of the receiver clock will never change
when the data is changing, and timing problems will be avoided.
When the differential signal changes, A is not equal to B and the counter
is reset. By sampling every 4 counts, we can gaurantee that we will correctly
receive every data bit that is sent. The one stipulation is that there
must be enough data transitions to re-synchronize the clocks every N bits.
N must be small enough to ensure that any difference in clock frequencies
between the transmitter and receiver doesn't cause an error. If the receiver
was much faster than the transmitter, it could sample more bits than were
actually sent. Bit stuffing is used to ensure that there are enough
data transitions.
: Also can the terminology used in this and future labs be more consistent? The term NRZI was used in interchange with differential, then differential value.
: Lastly, I find the ad-hoc introduction of unexplained terms, values, and buzzwords to be more confusing than enlightening.
I'll do my best, but get used to it. Most real specs are a lot worse than
this lab.
This is probably the hardest lab in the course to understand
because it comes before we've covered very much material in the lectures.
The remaining labs are technically more demanding, but you'll be a
lot more used to the terminology.
: Thanks