Re: Lab 1 - Size of circuit

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Posted by John Chappel on January 25, 1998 at 12:04:50:

In Reply to: problem solved? -> questions about lab1 posted by Maciej Kalisiak on January 24, 1998 at 15:25:02:

: I tried compiling my transmitter on an ugsparc machine
: (X11 over a 33.6k connection is painfully slow, but
: doable), and wouldn't you know it, it doesn't crash.
: It turns out that the problem is that it doesn't fit
: on the CPLD (crash->nice dianostic message :).

: This brings up a few questions:

: 1. For lab1, can we use the FPGA instead of the CPLD?
: (I've got 159 logic cells for my transmitter, when the
: CPLD only has 128; I suspect that even if I were to
: set the compilation preference for smallest code, I
: might be able to fit the transmitter on the chip, but
: not transmitter and reciever)

I expect this lab will require the FPGA.

: 2. Is it a correct assumption that when we download
: our program to the chip, it has to simultaneously
: transmit and recieve (ie. both the xmitter and reciever
: have to be on the chip)?

Yes. You need this to test your circuit.

: 3. Seeing as how this (size constraints) could be an
: even bigger problem in future labs, could we maybe
: get some pointers, design hints, on how to write
: VHDL code so that it generates small and compact logic
: on the chip (ie. how to generate smallest circuits
: during compile)?

Ask the TA's to review your code. The biggest way to reduce
circuit size is to carefully examine the architecture of
your datapath. Do you have more registers than you need?
Can you share some operators?

: Thanks.

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Comments:
: : I tried compiling my transmitter on an ugsparc machine : : (X11 over a 33.6k connection is painfully slow, but : : doable), and wouldn't you know it, it doesn't crash. : : It turns out that the problem is that it doesn't fit : : on the CPLD (crash->nice dianostic message :). : : This brings up a few questions: : : 1. For lab1, can we use the FPGA instead of the CPLD? : : (I've got 159 logic cells for my transmitter, when the : : CPLD only has 128; I suspect that even if I were to : : set the compilation preference for smallest code, I : : might be able to fit the transmitter on the chip, but : : not transmitter and reciever) : I expect this lab will require the FPGA. : : 2. Is it a correct assumption that when we download : : our program to the chip, it has to simultaneously : : transmit and recieve (ie. both the xmitter and reciever : : have to be on the chip)? : Yes. You need this to test your circuit. : : 3. Seeing as how this (size constraints) could be an : : even bigger problem in future labs, could we maybe : : get some pointers, design hints, on how to write : : VHDL code so that it generates small and compact logic : : on the chip (ie. how to generate smallest circuits : : during compile)? : Ask the TA's to review your code. The biggest way to reduce : circuit size is to carefully examine the architecture of : your datapath. Do you have more registers than you need? : Can you share some operators? : : : Thanks.

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