Re: Row and Collumn Addresses

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Posted by Michael van Dam on February 23, 1998 at 19:19:13:

In Reply to: Re: Row and Collumn Addresses posted by Wisnu Wurjantara on February 21, 1998 at 16:17:59:

: : I assume that the roles of the DRAM's row and collum
: : addresses are interchangable. That is, one can
: : interpret that DRAM_A[1-9] is the row address and
: : DRAM_A{10-18] is the collumn address, or the other
: : way around, DRAM_A[1-9] being the collumn address and
: : DRAM_A[10-18] the row address.
: : Is this right?

: There's a mistake in my question:
: I meant the Bus_Address[1-9] and Bus_Address[10-18] instead
: of the DRAM_A[1-9] and DRAM_A[10-18].

Switching columns and rows will simply change the physical
location in the memory chip where the data is stored.
Provided you use the same configuration of address lines
for both reading and writing, you can in fact scramble the
address wires as much as you like and the behaviour will
still be of a conventional memory.

(This may cause problems if you are using the 'page mode'
operation of the DRAM...)

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: : : I assume that the roles of the DRAM's row and collum : : : addresses are interchangable. That is, one can : : : interpret that DRAM_A[1-9] is the row address and : : : DRAM_A{10-18] is the collumn address, or the other : : : way around, DRAM_A[1-9] being the collumn address and : : : DRAM_A[10-18] the row address. : : : Is this right? : : There's a mistake in my question: : : I meant the Bus_Address[1-9] and Bus_Address[10-18] instead : : of the DRAM_A[1-9] and DRAM_A[10-18]. : Switching columns and rows will simply change the physical : location in the memory chip where the data is stored. : Provided you use the same configuration of address lines : for both reading and writing, you can in fact scramble the : address wires as much as you like and the behaviour will : still be of a conventional memory. : (This may cause problems if you are using the 'page mode' : operation of the DRAM...)

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