Talk 2.1: 9:30AM–10:45AM
| Session Name: | Advances in Integrated Circuit Design |
| Session Time: | 9:30AM–10:45AM |
| Author Name: | Ahmad Darabiha |
| Author Email: | ahmadd@eecg.utoronto.ca |
| Talk Title: | Efficient VLSI implementation for low-density parity-check decoders |
| Slides: | 2-1.ppt |
| Abstract: | Low-density parity-check (LDPC) codes have been recently adopted for several digital communication standards due to their high error correction performance and parallel decoding architecture. However, the lack of regularity in the graph of high-performance LDPC codes imposes serious challenges for efficient decoder hardware implementation. In this presentation we describe a bit-serial message-passing technique that reduces the decoder implementation complexity without affecting the error correction performance. |
| Research Group: | Electronics |
| Degree Program: | Ph.D. |
| Author Bio: | Ahmad Darabiha is a Ph.D. candidate in the Department of Electrical and Computer Engineering at the University of Toronto under the supervision of Prof. Chan Carusone and Prof. Kschischang. He received his B.Sc. degree from Sharif University of Technology, Iran, and his M.A.Sc. degree from University of Toronto both in electrical engineering in 1998 and 2002, respectively. His research interests lie in the areas of VLSI circuits for signal processing, channel coding and computer vision. |