Talk 2.7: 9:30AM–10:45AM
| Session Name: | Advances in Integrated Circuit Design |
| Session Time: | 9:30AM–10:45AM |
| Author Name: | Hratch Mangassarian |
| Author Email: | hratch@eecg.toronto.edu |
| Talk Title: | Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability |
| Slides: | 2-7.ppt |
| Abstract: | Disproportionate instantaneous power dissipation may result in unexpected power supply voltage fluctuations and permanent circuit damage. Therefore, estimation of maximum instantaneous power is crucial for the reliability assessment of VLSI chips. Circuit activity and consequently power dissipation in CMOS circuits are highly input-pattern dependent, making the problem of maximum power estimation computationally hard. This work proposes a novel pseudo-boolean satisfiability based method that reports the exact input sequence maximizing circuit activity in combinational and sequential circuits. The method is also extended to take multiple gate transitions into account by integrating delay information into the pseudo-boolean optimization problem. An extensive suite of experiments on ISCAS85 and ISCAS89 circuits confirms the efficiency and robustness of the approach compared to simulation based techniques and encourages further research for low-power solutions using boolean satisfiability. |
| Research Group: | Computer |
| Degree Program: | M.A.Sc. |
| Author Bio: | Hratch Mangassarian received his B.Eng. degree in Computer and Communications Engineering with high distinction from the American University of Beirut, Beirut, Lebanon, in 2005. He is currently pursuing his M.A.Sc. degree at the University of Toronto, Toronto, ON, Canada. His areas of interest include SAT, PB-SAT, QBF, and their applications to diagnosis and verification of digital circuits and other CAD problems. |