Talk 5.5: 1:30PM–2:45PM
| Session Name: | Computer Architectures, Compilers and Programming Models |
| Session Time: | 1:30PM–2:45PM |
| Author Name: | Martin Labrecque |
| Author Email: | martinl@eecg.utoronto.ca |
| Talk Title: | Custom Programmable Parallel Processors for Packet Processing |
| Slides: | 5-5.ppt |
| Abstract: | With the growing demand for online services, the computing needs of the Internet are expanding rapidly. While the most basic form of processing to be applied to a packet is routing, there is a lot of interest in the research and industry for more advanced packet processing such as content-based routing and intrusion detection. To effectively fulfill such diverse and changing needs, the packet processing should be defined in software and should be performed on a platform that can handle multiple packets at the same time in order to achieve a high throughput. To be able to create an optimized custom solution for an application and to benchmark the resulting processor on a real network, we use an FPGA (a chip consisting of programmable logic components and programmable interconnects) to implement a packet processing node. Our focus is on (i) studying processor architectures that exploit most efficiently the FPGA resources to provide the best throughput; (ii) providing a compiler infrastructure that, in conjunction with the hardware, eases the parallelization of an application. |
| Research Group: | Computer |
| Degree Program: | Ph.D. |
| Author Bio: | Martin Labrecque is a Ph.D. student in the Computer engineering group at the University of Toronto. He did his Master's at the University of Toronto and his B. Eng. at Ecole Polytechnique of Montreal. His research interests include co-design, reconfigurable architectures, artificial intelligence and robotics. |