Talk 5.7: 1:30PM–2:45PM
| Session Name: | Computer Architectures, Compilers and Programming Models |
| Session Time: | 1:30PM–2:45PM |
| Author Name: | Wei Zhang |
| Author Email: | weizer@eecg.toronto.edu |
| Talk Title: | Portable and Scalable Linear Equation Solver on FPGA |
| Slides: | 5-7.pdf |
| Abstract: | FPGA design is hard and time consuming. It often requires designers to implement everything from scratch. Also, once a design has been created for one specific FPGA, the same design cannot be easily transferred to another FPGA. The goal of the research is to provide portability and scalability for hardware. This research will develop a tool to generate a linear equation solver for different FPGAs. Given the area and resources available on the targeted FPGA, the best performance design in terms of speed will be generated. The generated design will be able to scale with the capabilities of the FPGA, taking advantage of the hard arithmetic units and memories on the FPGA. This research can be extended by implementing more algorithms and will be the first step into creating a hardware library of useful functions to facilitate hardware design. |
| Research Group: | Computer |
| Degree Program: | M.A.Sc. |
| Author Bio: | Wei Zhang is a master’s candidate in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering. His research interest includes the use of FPGA in supercomputing applications and automating hardware design. Zhang received a BASc in computer engineering from University of Waterloo. Contact him at weizer@eecg.toronto.edu. |