DDR SDRAM and the TM-4

Table of Contents

  1. DDR SDRAM Background Information
  2. TM-4 DDR SDRAM Structure
  3. Block Memory Controller
  4. Advanced TM-4 Memory Data

  1. DDR SDRAM Background
  2. DDR SDRAM is a dynamic ram standard that is designed to provide high memory depth and bandwidth. This section will provide the basic DDR SDRAM background necessary to effectively use the TM-4's memory subsystem. In particular the memory organization will be presented, followed by a description of how both reads and writes are performed.

    1. DDR SDRAM Memory Organization
    2. Addressing memory in a DDR SDRAM memory dimm requires four separate addresses:
      In a DDR SDRAM dimm there are usually two memory chips connected in parallel, with only their chip enable signals being unique. This configuration allows the two chips to share address and data lines. By selectively asserting only one chip enable single at a time, this configuration allows twice the memory depth compared with only a signal chip. The highest level of the memory addressing hierarchy controls these chip enable signals. This addressing level is called the chip selects.

      Figure 1: Internal DDR SDRAM memory chip block diagram
      DDR SDRAM Memory Organization

      The remaining three addressing levels all take place within a single memory chip. Figure 1 shows a simplified block diagram of the internals of a DDR SDRAM memory chip.

      At the core of the memory chip are four 2D memory array banks. Each of these memory banks is addressed by both a row and column address. To understand why this memory structure was selected it is necessary to first understand the process of reading from one of the 2D memory arrays.

      To read from the 2D memory array involves several steps. The first step involves selecting which row in the memory array to address. This is accomplished by issuing an ACTIVE command to the memory. This results in the memory array outputing an entire row of data via the sense amplifiers, shown in figure 1. At this point the memory chip is ready to accept read commands. These read commands include a column address, which is decoded and used to select which piece of data, currently outputted by the sense amplifiers, to read. Once the transaction is completed the 2D memory array can be returned to an idle state. This is accomplished by issuing a PRECHARGE command to the memory.

      The need to both activate and precharge the 2D memory array means that data can not be transmitted on every clock cycle, since the memory bank is busy handling other tasks. In order to provide a method to mask the time required to activate and precharge the memory array, DDR SDRAM memory chips contain four independent banks of memory. The idea is that while a given bank is being activated or precharged, transactions can still occur on the remaining banks.

    3. DDR SDRAM Memory Reads
    4. Under construction

    5. DDR SDRAM Memory Writes
    6. Under construction

    7. Additional Information
    8. DDR SDRAM Memory Module Manufacturers

      Kingston Technology


      Micron 512Mb DDR SDRAM chip datasheet
      Micron 1GB DDR SDRAM module datasheet

      Applicable Application Notes

      Micron TN-46-05 General DDR SDRAM Functionality
      Micron TN-46-07 DDR333 Memory Design Guide for 2-DIMM Unbuffered Systems

      Other Relevent Documents

      Micron DDR SDRAM Functionality and Controller Read Data Capture
      Micron DDR SDRAM Timing Revision Information
      Altera DDR SDRAM Controller MegaCore User Guide
      Micron DDR System Design Consideration Slides
      Fairchild DDR SDRAM Signaling Design Notes

      SSTL-2 Termination Regulators

      LP2995 National 1.5A DDR Termination Regulator
      LP2996 National 1.5A DDR Linear Termination Regulator w/Shutdown
      MAX1957 Maxim IC 4A DDR Switching Termination Regulator

  3. TM-4 DDR SDRAM Structure
  4. Each of the four FPGAs of the TM-4 are connected to 2 independent DDR SDRAM memory modules. The board is designed to support modules upto 4GB in density, providing they are organized in x8 form (8 DQ signals per DQS). The standard TM-4 configuration contains 8 1GB registered memory modules; unregistered modules have also been verified to operate. Specifications for the standard memory modules are as follows:

    A short-form datasheet for the Kingston memory can be found here.
    A long-form datasheet of a similar, but non identical, module can be found here .

  5. Block Memory Controller
  6. Note: A newer DDR SDRAM controller is available here

    The TM-4 example directory includes a DDR SDRAM controller circuit which is designed to abstract away most of the complexity involved in interfacing with DDR SDRAM. The core is optimized to perform block transfers of consecutive data and is not appropriate for random memory access patterns. Figure 2 shows a block diagram of the memory controller.

    Figure 2: Memory Controller Block Diagram
    Memory Controller Block Diagram

    The entire controller system contains four different parts: The DDR SDRAM memory controller logic, an arbitor, and two dual ported SRAM. The SRAMs are used as on-FPGA memory buffers and are the sole data communication channel with the DDR SDRAM. The arbitor allows user requests for reads and writes between the SRAMs and the DDR SDRAMs to be submitted to the memory controller logic, and the controller logic contains all the necessary circuitry to initialize the memory, perform refreshes, and perform burst transactions.

    The SRAM buffers are both independent true dual ported buffers. This means that the clocks used to access these buffers need not be related to the highspeed DDR SDRAM clock, and in addition, these clocks need not be related to each other either. Although the output port of these buffers are both configured to 16384x36 in the example circuit, the arrangement could easily be changed to any other Quartus supported organization (ie 8192x72, etc).

    The arbitor circuit is designed to transfer control requests from the user clock domain to the DDR SDRAM controllers clock domain, while also sharing access to the memory. The algorithm employed is one in which a request on interface A always is serviced before a request on interface B. There is no guarantee that interface B will ever gain access to the memory. Once again this could be easily changed by the user.

    The control signals necessary to initiate a transaction between the SRAM and the DDR SDRAM are listed below:

    The first two signals are asynchronous handshaking signals. TransrequestA is asserted by the user circuit when they wish to request a transaction. This signal is held asserted until such time as the arbitor asserts its transaction_completeA signal. At this time the user should deassert its transrequestA signal and must wait until the transaction_completeA signal is deasserted by the memory controller before another transaction can be initiated.

    The readwritenA signal specifies if the transaction is a read, if 1, or a write, if 0. The read/write is taken from the point of view of the DDR SDRAM. That is that a read means data is transfered from the DDR SDRAM to the on-FPGA SRAM buffer.

    The ddr_* signals specify what range of DDR SDRAM memory to access. ddr_addressA is a combination of the chip select, bank select, and row addresses described in the previous section. It is used to address a single row of the DDR SDRAM. The remaining address, ddr_start_blockA, and ddr_end_blockA, specify the where to start and stop the transfer in the specified row. The unit in which ddr_*_block is expressed in is one of 16 DDR SDRAM words (16x72bits). This means that a single row is divided into 128 different blocks. Figure 3 summarizes the block division information.

    Figure 3: DDR SDRAM Row Block Division
    An Entire SDRAM DDR Row2048 x 72bits
    Block Size16 x 72bits
    Total Blocks per Row128
    Smallest Transfer
    (Single Block)
    1152 bits
    144 bytes
    8 memory cycles
    Largest Transfer
    (128 Blocks)
    147456 bits
    18432 bytes
    1024 memory cycles

    The final control signal is the sram_start_addressA. This signal specifies what starting address in the SRAM to use for the requested transaction. This address is specified for the SRAM memory when configured in 4096x144 mode (since this is the mode that the DDR controller uses). To understand the mapping between the 144 bit wide port of the memory and the 36 bit wide user port consult the Altera documentation on dual ported memory.

    One final note in regards to the sram_start_addressA is that it is up to the designer to insure that there is sufficient space in the SRAM buffer to contain the entire data transfered between the DDR SDRAM. What I mean by this is that it is possible to set the sram_start_addressA to the last word of the SRAM buffer but request that the DDR controller transfer multiple words. This will result in unpredictable behaviour. It is not safe to assume that the sram address will wrap around to zero again.

  7. Advanced TM-4 Memory Data

  8. Table 1: DDR Bank 0A Board Timing Delays
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.68ns1.12ns
    DQ/DM/CB (F->D)0.46ns0.78ns
    DQS (D->F)0.72ns1.07ns
    DQS (F->D)0.47ns0.70ns
    Table 2: DDR Bank 0B Board Timing Delays
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.81ns1.19ns
    DQ/DM/CB (F->D)0.58ns0.84ns
    DQS (D->F)0.86ns1.22ns
    DQS (F->D)0.61ns0.84ns
    Table 3: DDR Bank 1A Board Timing Delays
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.67ns1.12ns
    DQ/DM/CB (F->D)0.45ns0.79ns
    DQS (D->F)0.71ns1.11ns
    DQS (F->D)0.44ns0.73ns
    Table 4: DDR Bank 1B Board Timing Delays
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.70ns1.26ns
    DQ/DM/CB (F->D)0.48ns0.98ns
    DQS (D->F)0.78ns1.29ns
    DQS (F->D)0.53ns0.92ns
    Board revision B target trace delays
    Table 5: DDR Bank 0A Board Timing Delays (Rev B)
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.70ns1.08ns
    DQ/DM/CB (F->D)0.48ns0.75ns
    DQS (D->F)0.73ns1.06ns
    DQS (F->D)0.48ns0.68ns
    Table 6: DDR Bank 0B Board Timing Delays (Rev B)
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.82ns1.17ns
    DQ/DM/CB (F->D)0.61ns0.83ns
    DQS (D->F)0.86ns1.18ns
    DQS (F->D)0.61ns0.81ns
    Table 7: DDR Bank 1A Board Timing Delays (Rev B)
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.70ns1.08ns
    DQ/DM/CB (F->D)0.48ns0.71ns
    DQS (D->F)0.75ns1.08ns
    DQS (F->D)0.48ns0.68ns
    Table 8: DDR Bank 1B Board Timing Delays (Rev B)
    GroupMin DelayMax Delay
    DQ/DM/CB (D->F)0.90ns1.08ns
    DQ/DM/CB (F->D)0.68ns0.92ns
    DQS (D->F)0.90ns1.12ns
    DQS (F->D)0.66ns0.85ns
    Detail delay information can be found here: Bank 0A, Bank 0B, Bank 1A, Bank 1B