Current Graduate Students

Sameh Attia, PhD
Safe context switching and novel debugging flows for FPGAs, particularly for datacenter applications.

Andrew Boutros, PhD (graduated with MASc in 2018)
More efficient FPGA architectures for machine learning.

Mohamed Elgammal, PhD
Applying machine learning to FPGA CAD.

Sarah Khalid, MASc Efficient CAD tools for FPGA placement.

Mohamed Ibrahim, MASc Multi-FPGA acceleration of CNNs.

Marius Stan, MASc CNN acceleration on Novel FPGAs.

Shuran Wang, MASc Robust optimization of photodynamic therapy (light-activated chemotherapy)

Kate Thurmer, PhD Flexible CAD tools for efficient implementation of FPGA designs and architecture exploration

Srivatsan Srinivasan, MASc Placement algorithms for FPGAs with embedded hard NoCs and multiple active dice

Charles Chen, MEng Optimizing the physical design of the HPIPE neural network acceleration with automatic floorplanning.

Former Graduate Students and Researchers

Fynn Schwiegelshohn, Post-doctoral Fellow Hardware-accelerated photonic simulation with FPGAs, with applications to PDT cancer treatment planning.

Abed Yassine, PhD
Developed PDT-SPACE a treatment planning CAD system for photodynamic therapy (PDT), a minimally invasive light-activated chemotherapy for cancer treatment.

Kevin Murray, PhD
Investigated new physical and timing CAD tools including placement and floorplanning, to allow efficient design of large applications and FPGA architecture invetigation.

Ibrahim Ahmed, PhD
Developed a robust dynamic voltage scaling system for FPGAs to save power.

Mathew Hall, MASc Efficient sparse CNN acceleration on FPGAs.

Tanner Young-Schultz, MASc Accelerating photonic calculations on CPUs, GPUs and FPGAs, with applications to PDT cancer treatment planning.

Mohamed Eldafrawy, MASc Enhancing FPGA architectures for efficient machine learning inference.

Sadegh Yazdanshenas, PhD
Novel circuits (MTJ, BRAM) for FPGAs, and efficient shells (with and without hard NoCs) for datacenter FPGAs, and secure multi-tenant FPGAs.

Kosoke Tatsumura, Visiting Researcher from Toshiba Corporation
MTJ-based FPGA BRAMs, and efficient RAM architectures for FPGAs.

Henry Wong, PhD
Research higher performance soft core processors for FPGAs, and build an x86 compatible soft core processor.

Jeff Cassidy, MASc
Developed a 3D simulation of photon absorption within arbitrary inhomogeneous material, for use in planning photodynamic cancer therapy.

Mohamed Abdelfattah, PhD
Investigated how networks on a chip (NoCs) can best be integrated with FPGA logic to form a new hybrid device. Now at Intel Corporation's Programmable Solutions Group.

Linda Shen, MASc Quantifying and mitigating voltage transients on FPGAs.

Mustafa Abbas, MASc
Improved latency insensitive design methods and clocking architecture evaluation tools for FPGAs.

Yasmin Afsharnezhad, MASc
Hardware acceleration of biophotonic calculations, to enable efficient treatment planning for photodynamic therapy.

Andrew Bitar, MASc
Researched new applications for FPGAs with embedded hard NoCs, and a CAD system for such FPGAs. Now at Intel Corporation's Programmable Solutions Group.

Oleg Petelin, MASc
Investigating new switch fabrics and switch evaluation tools for FPGAs.

Matthew An, MASc
Researching new parallel placement algorithms, and investigating how the transactional memory parallel processing paradigm can be applied to FPGA CAD.

Ehsan Nasiri, MEng
Evaluated new switch fabrics for interposer-based FPGAs. Now at Google, Waterloo.

Javeed Shaikh, MEng
Investigated "partition-then-place" CAD flows for interposer-based FPGAs. Now at Google, Mountain View, CA.

Rafat Rashid, MASc
Developed the hardware and compiler for an efficient FPGA overlay based on an application customized multi-threaded VLIW processor. Achieves 40% to 80% of the efficiency of OpenCL-based HLS, with 100x reduced recompilation time. Now at Index Exchange.

Charles Chiasson, MASc
Investigated novel electrical and architectural enhancements to FPGA interconnect in very advanced process technology. Now at Intel's Programmable Solutions Group.

Tim Liu, MASc
Investigated high-quality and scalable placement algorithms for very large circuits.

Wei Zhang
, MASc Developed a portable and scalable LU decomposition engine for FPGAs; this design easily adapts to and benefits from larger and faster FPGAs in the future.
Now at Xilinx.

Undergraduate Student Researchers

Matthew Walker, BASc, summer researcher, 2014 Visualizing FPGA architectures and arithmetic heavy benchmarks. Linda Shen, BASc, summer researcher, 2014 COFFE (FPGA circuit optimizer) enhancements and FinFET optimization. Andre Hahn Pereira, Visiting undergraduate researcher from University of Sao Paolo, Brazil, 2013
Architecture and CAD for Silicon-Interposer-Based FPGAS

Ange Yaghi, BASc, summer researcher, 2013
Embedding NoCs in FPGAs: Modeling and Simulation

Longyu Wang, BASc, summer researcher, 2013
Visualizing FPGA architectures

Jerry She, BASc, summer researcher, 2013
Improving CAD timing optimization for designs with complex timing.

Suya Liu, BASc, summer researcher, 2012
Worked to enable large and realistic benchmark designs to pass into academic flows, so academics can work on state-of-the-art problems. This involved three parts: modeling the Stratix IV architecture within VPR, obtaining large benchmark circuits, and upgrading the vqm2blif CAD flow that converts these circuits to an academic format.

Thien Yu, BASc, summer researcher, 2012
Upgraded VPR's placement engine to be more efficient by using "incremental" update techniques. Added support for carry chains to VPR, starting with a flexible description of these chains, through to upgrading the placement engine to respect the constraints imposed by such chains.

Michael Wainberg, BASc, summer researcher, 2012
Added multi-clock timing analysis to VPR, which is crucial in today's large, complex circuits. Investigated how best to optimize circuits with multiple timing constraints, and upgraded all optimization in VPR to be multi-clock aware.

Scott Whitty, BASc, summer researcher, 2011
Develop a CAD flow to allow large benchmark circuits to be analyzed and synthesized to basic components by an industrial tool flow, and then translate these intermediate results into circuits suitable for academic research flows.

Undergraduate Engineering Science Theses

Scott Whitty, Many Heads Make Great Work: Parallelizing Decision-Based Optimization Algorithms, 2013 - 2014

Mark Sutherland, Security at What Price: Investigating the Hardware Cost of Physical Layer Security in MIMO Systems, 2013 - 2014.

Undergraduate Design Projects

Emil Salavat, Li Chen and Yu Wu, 2014 - 2015
An arbitrary geometry, tetrahedral mesh Monte Carlo photon simulator optimized for GPUs

Naif Tarafdar and Jordan Zannier, 2013 - 2014
High-performance Monte Carlo photon simulations in OpenCL on CPUs, GPUs and FPGAs

Zohair Massoud and Bilal Afzar, 2013 - 2014
A Portable Piano Tutor on a Cell Phone

Ke Deng, Saiquan Zhang, and Zimo Li, 2012 - 2013
Develop a high-definition video-effects engine on an FPGA.

Kiril Pashin and Hoi-Ki Tong , 2012 - 2013
Investigate FPGA routing algorithms to improve performance, and resolve hold time violations.

Jack Wu, Qian Sun, and Shi Zhang , 2012 - 2013
Develop a voice controlled browser that reads out web pages for an Android phone.

Brian Pelingon and Venneti Prasanna , 2012 - 2013
Develop a cell-phone based client server system to find and record available parking.

Ehsan Nasiri, Rafat Rashid and Saurabh Verma, 2011 - 2012
Develop an LU decomposition engine in OpenCL, and port it to GPUs, multi-core CPUs and FPGAs. Compare performance, and evalute how significant the code changes are to achieve high performance on each platform (performance portability).

Fredrich Ombico and Hani Abdo, 2011 - 2012
Develop a multiplayer online game on Android mobile devices.

Canna Wen, Rafal Dittwald and Clifford Lau
Develop an online version of the Diplomacy multiplayer strategy game to be played on mobile devices.

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