• General Introduction - No notes available: An overview of the evolution of computer architectures including pipelining, superscalar and Out-of-Order execution, Very Long Instruction Word, Single Instruction Multiple Data, Vector, Dataflow, Graphics processor.
• What is architecture and what are the underlying technology forces that have an impact on what is the best machine possible one can build
• Homework #1: Prepare an index card with your photo and a brief description of your background.
• Reading: Whenever you have time I suggest you read the following two overview papers:

1. Microarchitectural Innovations: Boosting Processor Performance Beyond Technology Scaling, Moshovos, Sohi, IEEE Proceedings, 2002
2. Instruction Level Parallel Processing: History, Overview, and Perspective, B. Rau and A. Fisher (local copy)

• Background: Building a Simple Processor:
• Single-Cycle Implementation Datapath and Control
• Multi-cycle Implementation: Datapath, Control

• Pipelining Execution: Key Concepts, relation, real-word examples (Alpha processors)
• Support for Speculative Execution
• Lecture Notes:* Pipelining, Superscalar
• Reading: Implementation of precise interrupts in pipelined processors, J. Smith and A. Pleszkun, IEEE Transactions on Computers, 1988, first appeared in Int'l Symposium on Computer Architecture, 1986

• Superscalar Execution: Key Concepts, relation, real-word examples (Alpha processors)
• Support for Speculative Execution
• Lecture Notes:* Support for Speculative Execution -- Updated starting at slide 23, Superscalar

• Out-of-Order Execution: Key Concepts
• Register Renaming
• Lecture Notes:* OOO Execution

• Control Flow Speculation
• Lecture Notes:* Control Flow

• Scheduler Optimizations
• Lecture Notes:* Scheduler

1. Focusing Processor Policies via Critical-Path Prediction, B. Fields, S. Rubin and R. Bodik, Proceedings of the Annual International Symposium on Computer Architecture, 2001.

1. rePLay: A Hardware Framework for Dynamic Optimization, S. J. Patel, S. S. Lumetta, IEEE Transactions on Computers, June 2001.

• Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt, Proceedings of the Annual International Conference on High-Performance Computer Architecture, 2003.

• Continual Flow Pipelines, Srikanth T. Srinivasan Ravi Rajwar Haitham Akkary Amit Gandhi Mike Upton, Proceedings of the ACM Symposium on Architectural Support for Operating Systems and Programming Languages, 2004.

• Slipstream Processors: Improving both Performance and Fault Tolerance, Karthik Sundaramoorthy, Zach Purser, Eric Rotenberg, Proceedings of the Annual International Symposium on Architectural Support for Programming Languages and Operating Systems, 2000.

• A fully associative software-managed cache design, Erik G. Hallnor, Steven K. Reinhardt, Proceedings of the Annual International Conference on Computer Architecture, 2000.

• The V-Way Cache: Demand Based Associativity via Global Replacement, Moinuddin K. Qureshi, David Thompson, and Yale N. Patt, Proceedings of the Annual International Conference on Computer Architecture, 2000.

• Adaptive Insertion Policies for High Performance Caching, Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely, and Joel Emer, Proceedings of the Annual International Conference on Computer Architecture, 2007.

• Emulating Optimal Replacement with a Shepherd Cache, K. Rajan and R.Govindarajan, Proceedings of the Annual International Conference on Microarchitecture, 2007.

• Memory Dependence Prediction Using Store Sets, G. Chrysos and J. Emer, Proceedings of the Annual International Symposium on Computer Architecture, 1998.
• Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors, A. Moshovos and G. Sohi, Proc. of the Conference on High Performance Computer Architecture, Feb. 2000.
• An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches, C. Kim, D. Burger, S. W. Keckler, Proc. of the Conference on Architectural Support for Programming Languages and Operating Systems, 2002.
• Multiscalar Processors, Gurindar Sohi, S. Breach, T. N. Vijaykumar, Proceedings of the Annual International Conference on Computer Architecture, 1995.

• DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, Todd Austin, Proceedings of the Annual International Symposium on Microarchitecture, 2000.
• Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Toan Pham, Rajeev Rao, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge, and Krisztián Flautner, , 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003.
• Techniques to Reduce the Soft Errors Rate in a High-Performance Microprocessor, Christopher Weaver, Joel Emer, Shubhendu S. Mukherjee, and Steven K. Reinhardt, Proceedings of the Annual International Conference on Computer Architecture, 2004.
• Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth., Anne Bracy, Prashant Prahlad and Amir Roth. 37th International Symposium on Microarchitecture (MICRO-37), Dec. 4-8, 2004.
• Cache Bursts: A New Approach for Eliminating Dead Blocks and Increasing Cache Efficiency, Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger, International Symposium on Microarchitecture , 2008.

Read this on your own – no presentation will be given:

* Lifetime Reliability: Toward an Architectural Solution., Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers, IEEE Micro 25(3): 70-80 (2005).