Question 9

Consider the two-bus architecture shown, and the following instruction.

add.w	d5,(a3)+

Give the steps and control signals for implementing the instruction in the table. Use ONLY the following control signals:

IRin, PCinA, PCinB, PCout, Zin, Zout, d5inA, d5inB, d5out, a3inA, a3inB, a3out, YinA, YinB,select Y, select 0, select 1, select2, MARinA, MARinB, MDRinA, MDRinB, MDRout, ALUadd, READ, WRITE, WMFC, END

10 places are provided for your answer – use only the steps you need

Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Step 8
Step 9
Step 10

Step 1 WMFC, PCout, MARinA, READ, select 2, ALUadd, PCinB

Step 2 WMFC, MDRout, IRin

Step 3 a3out, MARinA, READ, select 2, ALUadd, a3inB

Step 4 d5out, YinA

Step 5 WMFC, select Y, MDRout, ALUadd, MDRinB, WRITE, END

This is the most efficient solution

SOLUTION NOTES:

WMFC must appear in a step AFTER the corresponding READ or WRITE
- For a READ, it is most efficient if the WMFC appears in the step where the value returned from memory is first used
The final WRITE requires a WMFC. There are two correct possibilities for where:
- In a step after the final write
- In the very first step (implying that there would have to be a WMFC in the very first step of the implementation of every instruction)

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Computer Architecture Questions

Question 9

Step 1	WMFC, PCout, MARinA, READ, select 2, ALUadd, PCinB
Step 2	WMFC, MDRout, IRin
Step 3	a3out, MARinA, READ, select 2, ALUadd, a3inB
Step 4	d5out, YinA
Step 5	WMFC, select Y, MDRout, ALUadd, MDRinB, WRITE, END