| Main | Assembly Programming | Input/Output | Memory | Computer Architecture | Advanced Topics |
Give a block diagram for a 2M x 16 memory using 256K x 8 SRAM chips connecting to a processor with a 24 bit address and a byte-addressable memory space (no cache is present). The memory should be connected starting at address $000000. You should show which address lines are used and their connections to the chips. You do not need to give details of the inner working of the memory chips or any bus synchronization information, but the addressing should be handled in enough detail to make your circuit obvious. Assume each chip has connections as shown in the diagram at right.
Need 2 chips ‘wide’ to handle data bus width. Need 8 chips ‘deep’ to get memory size.
Address must handle 2M therefore need 22 bits. LSB is not used (16 bit data but byte-addressable). Bits 1-3 select one of the rows of the memory through a demux. 10+8 bits (bits 4-21) go to the chips. Bits 22-23 must be zero (a decoder or NOR gate).