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A memory system has the following performance characteristics:
Cache Tag Check time: 1ns
Cache Read Time: 1ns
Cache Line Size: 64 bytes
Memory Access time (Time to start memory operation): 10 ns
Memory Transfer time: 1ns/memory word
Memory Word: 16 bytes
The processor is pipelined and has a clock cycle of 500 MHz. The memory operation occupies one stage in the pipeline. If it takes longer, the pipeline is stalled.
What is the memory stall time for a program that performs 100 memory reads of which 90 hit in the cache and 10 miss. Memory stall time is defined as the amount of time the pipeline spends stalled due memory operations.
140ns
90 hits -> 0 stall; 10 misses -> (15+1-2)*10=140 ns stall time
Note: The +1 is because the stall time must be in multiples of clock cycles. The –2 is because the first 2 ns are part of the normal (unstalled) cycle