discrepancy of timing diagram with 68K specs

[ Follow Ups ] [ Post Followup ] [ ECE 532 Discussion Area ] [ FAQ ]

Posted by Maciej Kalisiak on February 15, 1998 at 16:14:11:

I was wondering whether it is just me, or is there
really a problem with the timing diagram shown in lab2?

According to the 68K BUS TIMING specs, and
according to what we covered in class, the 68K
samples both the DTACKn and the DATA on 1 to 0
transitions, yet the lab diagram shows it as a 0 to 1
transition.

Furthermore, some of the numbers don't match
the 68K BUS TIMING specs (or maybe I'm
reading them wrong).

The specs seem to say that for 10MHz, the setup time
for the DATA is (#27)10ns, while the diagram shows
35ns.


Follow Ups:

Post a Followup

Name:
E-Mail:

Subject:

Comments:

Optional Link URL:
Link Title:
Optional Image URL:

[ Follow Ups ] [ Post Followup ] [ ECE 532 Discussion Area ] [ FAQ ]