Re: discrepancy of timing diagram with 68K specs

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: : I was wondering whether it is just me, or is there : : really a problem with the timing diagram shown in lab2? : : According to the 68K BUS TIMING specs, and : : according to what we covered in class, the 68K : : samples both the DTACKn and the DATA on 1 to 0 : : transitions, yet the lab diagram shows it as a 0 to 1 : : transition. : You are correct... sampling is performed on the falling : edge. However, the details of this are not important and : you need not worry about the bus clock and where its : edges occur. Just ensure that you meet all the timing : requirements between *edges of the handshake signals*. : : Furthermore, some of the numbers don't match : : the 68K BUS TIMING specs (or maybe I'm : : reading them wrong). : : The specs seem to say that for 10MHz, the setup time : : for the DATA is (#27)10ns, while the diagram shows : : 35ns. : (Note that #27 refers to the tiny interval to the right of : the number 27 in the diagram.) : If you look at the 'footnote' for #27, (i.e. fn #6), you : will see that there is some interaction between the : various specs. In this case, it says if you meet #47 for : the DTACK, then you need only meet #27 for the DATA. : If you don't meet #47, you must meet #31 for the DATA. : (I do not know the internal details of where these two : different setup times -- 10 ns and 35 ns -- come from.) : In general, I would suggest not worrying about the position : of the bus clock edges in this lab. Thus just make sure : you meet the #31 requirement... : Mike

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