Talk 8.2: 3:15PM–4:15PM
| Session Name: | Novel FPGA Architectures and Advances in CAD Tools |
| Session Time: | 3:15PM–4:15PM |
| Author Name: | Tomasz S Czajkowski |
| Author Email: | czajkow@eecg.toronto.edu |
| Talk Title: | Using Negative Edge Triggered FFs to Reduce Glitching Power |
| Slides: | 8-2.ppt |
| Abstract: | This talk presents an algorithm for reducing dynamic power dissipated by Field-Programmable Gate Array (FPGA) circuits. The algorithm uses a fast probability based model to estimate glitches on wires in a circuit and then inserts negative edge triggered Flip-Flops (FFs) at outputs of Lookup Tables (LUTs) that produce glitches. A negative edge triggered FF maintains the logic value produced by the LUT in the previous cycle for the first half of the clock period, filtering glitches that occur at the output of the LUT. The power dissipation is lowered by reducing the number of transitions that propagate to the general routing network. We applied the algorithm to a set of benchmark circuits implemented on a commercial FPGA, Altera's Stratix II. The results obtained using Quartus II 5.1 CAD tool show a reduction in dynamic power dissipation by 7% on average and up to 25%. |
| Research Group: | Computer |
| Degree Program: | Ph.D. |
| Author Bio: | Tomasz S. Czajkowski received his BASc and MASc from the University of Toronto in 2001 and 2004, respectively. He is currently a PhD candidate at the University of Toronto, under the supervision of Professor Stephen D. Brown. His work focuses on physical synthesis for modern FPGA devices. |