Session 8: 3:15PM–4:15PM
| Session 8: Novel FPGA Architectures and Advances in CAD Tools | |
| 1. | Andrew Ling, FBDD: Towards Scalable Synthesis. |
| 2. | Tomasz S Czajkowski, Using Negative Edge Triggered FFs to Reduce Glitching Power. |
| 3. | Mark Fang, FPGA Interconnect Modelling: with Simple and Intuitive Equations. |
| 4. | Ian Kuon, Area-Delay Trade-offs in the Design of FPGAs. |
| 5. | Peter Jamieson, Hard Crossbars on FPGAs. |
| 6. | Navid Toosizadeh, Application-driven Synthesis for Asynchronous Systems. |