Talk 8.5: 3:15PM–4:15PM
| Session Name: | Novel FPGA Architectures and Advances in CAD Tools |
| Session Time: | 3:15PM–4:15PM |
| Author Name: | Peter Jamieson |
| Author Email: | jamieson@eecg.toronto.edu |
| Talk Title: | Hard Crossbars on FPGAs |
| Slides: | Slides not submitted |
| Abstract: | More and more hard circuits are being added to FPGAs such as hard multipliers, memories, and I/O blocks. These circuits improve the area, speed, and power of an FPGA for many of the designs that target them. One approach to continue improving FPGAs is to add more types of these hard circuits, but because only a small number of designs would use these structures and get a benefit it doesn't make sense to add these circuits. In this talk, we use our previous idea on Shadow Clusters to re-examine if a structure like a hard crossbar could be added to an FPGA. |
| Research Group: | Computer |
| Degree Program: | Ph.D. |
| Author Bio: | Biography not submitted. |