Talk 8.3: 3:15PM–4:15PM
| Session Name: | Novel FPGA Architectures and Advances in CAD Tools |
| Session Time: | 3:15PM–4:15PM |
| Author Name: | Mark Fang |
| Author Email: | fang@eecg.utoronto.ca |
| Talk Title: | FPGA Interconnect Modelling: with Simple and Intuitive Equations |
| Slides: | 8-3.ppt |
| Abstract: | A key issue in the architecture of Field Programmable Gate Arrays (FPGAs) is the design of their programmable interconnect. When designing programmable interconnect, an architect needs to understand how much interconnect resources (wires and programmable switches) to allocate and how to trade off one type of interconnect resource for another. Our work aims at creating a model for the modern island-style programmable interconnect, which can be used by an FPGA architect to determine and make tradeoffs of interconnect resources. This model is in the form of simple and intuitive equations that can be used for quick analysis in early architecture design stages. The inputs to the model are a few simple circuit parameters and a set of important architectural parameters capable of describing a large architectural space. We have found simple equations that predict required wire count with 5.1% average error for bi-directionally wired interconnect architectures using our benchmarks, and we are currently creating similar equations for modern uni-directionally wired /single-driver interconnect architectures. |
| Research Group: | Computer |
| Degree Program: | M.A.Sc. |
| Author Bio: | Mark Fang was born in Wuhan, China, on September 26, 1982. He received the B.A.Sc. degree (with distinction) in computer engineering (hardware option) from the University of Toronto in 2005. He is currently pursuing the M.A.Sc. degree at the same university. His research interests include architecture and CAD for Field Programmable Gate Arrays (FPGAs), in particular interconnect prediction and place and route tools development for latest FPGA architectures. |