Talk 8.4: 3:15PM–4:15PM
| Session Name: | Novel FPGA Architectures and Advances in CAD Tools |
| Session Time: | 3:15PM–4:15PM |
| Author Name: | Ian Kuon |
| Author Email: | ikuon@eecg.utoronto.ca |
| Talk Title: | Area-Delay Trade-offs in the Design of FPGAs |
| Slides: | Slides not submitted |
| Abstract: | The capabilities of field-programmable gate arrays (FPGAs) continue to improve and this has enabled them to serve an ever wider range of markets. Due to this breadth, it is no longer possible for a single FPGA family to adequately serve the full range of markets and, instead, multiple FPGA families that make different cost vs. performance trade-offs are now necessary. Conventionally, the focus in the development of these new FPGA families has been on high-level architectural parameters such as look-up table (LUT) size, cluster size and routing topology. However, the electrical implementation of a given architecture can significantly alter its cost and performance. This work combines both the high-level architectural exploration with the lower level electrical implementation to determine the range of cost and performance trade-offs that are possible. We find that different points in the cost vs. performance design space require different architectural parameters. As well, we measure the magnitude of the performance and cost trade-offs possible when both architectural and electrical parameters are varied. |
| Research Group: | Computer |
| Degree Program: | Ph.D. |
| Author Bio: | Biography not submitted. |