The Circuit Characterization and Generation Project
at the University of Toronto



The principles in the project are Michael Hutton, Jonathan Rose and Derek Corneil.


Paul Kundarewich is working on new improvements, and also gave GEN a good re-write, including a port to the PC from the original unix base.  Expect GEN 3.1 to be obsolete soon.


Most of the software (CAD) problems and hardware architecture problems encountered in the design of ASIC and FPGA devices require benchmark circuits. However, these are hard to come by, and when they do exist they are often the wrong size, or we don't have enough at the size we want, or they are missing some of the properties we want.

Research Overview

This project is an attempt to deal with this difficulty. Our approach involves three phases. All work by other researchers that we mention here is attributed in the related work page.


I.                    Analyze existing benchmark circuits. We determine graph-theoretic models, characteristics and properties of circuits which make them "different" from arbitrary (random) graphs. We have used primarily the MCNC LGSynth93 benchmark circuits, but we have had some access to industrial circuits from companies such as Altera. The analysis phase of the project has been implemented in a software tool called CIRC.


II.                 Generate circuits which have the correct type of characteristics to be typical digital circuits. We have algorithms to generate combinational and sequential circuits, implemented in a tool called GEN.



III.                Validate that the circuits generated by GEN are realistic by performing placement and routing, and contrasting the results with both real benchmark circuits and to random graphs. For more detail, see the papers (below).


Both CIRC and GEN are available for use in the public domain. You can download the software and documentation. We also provide some example circuits which were produced by GEN.

Implementation Details

The input to CIRC is a netlist in BLIF (Berkeley Logic Interchange Format) format. We assume that all netlists are synchronous sequential designs technology mapped to 4-input LUTs with a single clock and only D-type flip-flops.

The output of GEN is a netlist, also in BLIF. CIRC is able to read this netlist and filter the output into a number of different formats, including Xilinx XNF, Altera AHDL/TDF, the .net format referred to by Chuck Alpert's partitioning page, and a primitive form of Verilog. Read the documentation for more detail. See the "Research Publications" section to the right to view or download papers about our research.