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ECE532S: Digital Systems Design

Paul Chow

Spring 2011

This page is used to provide most of the information and links that mainly support the lab material. Blackboard will only be used for announcements, the discussion board, and content that needs password access, like marks.

This page can be viewed directly at

A special thanks to Xilinx for the donations of hardware and software that make the labs possible.

Course Description

Expected Background


Project and Lab Stuff

Past Projects

Project Tips

Things to Know

Checking Disk Quotas
To check your current disk space usage and limits on the ug machines, use the command quota -s.

Directory and File Names
Do not have any directories or filenames in your path that have spaces in them. For example, do not have your project directory in the folder called ``My Documents''. To be safe, it would also be wise to take the same precaution when installing the tools.

512 MB DIMM Memory Errors
If you have a board with 512 MB DIMMs, you will need to make some changes to avoid read errors. Find the fix here.

Documentation for Hardware and Software

This is a site dedicated to the EDK tools and the Xilinx boards that we are using. Labs/tutorials and other useful documentation for the tools and hardware used in this course are available here.

For Spring 2011, we will be using the 10.1 version of the Xilinx tools. Note that this is the last version of the tools that support the FPGA on the boards we use.


Virtex-II Pro Data Sheets
This is the Xilinx web page for the Virtex-II Pro data sheets. You should have a look through Module 2. In particular, pay attention to the Configurable Logic and the 18K Block SelectRAM sections. Note that the basic Virtex-II and Virtex-II Pro logic block and memory architectures are pretty much the same. The Virtex-II Pro comes with added features, such as the embedded Power PC.

Xilinx Clock Management Application Notes
XAPP132 starts out with a basic description of the use of the Xilinx DCM.

Stratix Data Sheets
This is the Altera web page for the Stratix data sheets, which is a similar generation device to the Virtex-II and Virtex-II Pro devices. You should have a look through Volume 1, Chapter 2. In particular, look at the sections on the Logic Array Blocks, the Logic Elements and the TriMatrix Memory.

A Design Example

This is a simple example illustrating good design practices. You should study it and emulate it!

Lecture References

There is no textbook for this course. When available, you will be provided with handouts or links to material here or in the course handouts section.

Altera Custom Instructions

Xilinx FSLs
Attaching hardware to the MicroBlaze.

Timing Analysis
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Hall, Hall and McCall, Wiley. Chapter 8 is most directly relevant to the lectures. Chapter 9 gets more into setting up spreadsheets to do the computations. Available through UofT library online

Clock Domains and Synchronization
Digital Systems Engineering, Dally and Poulton, Cambridge. Chapter 10.

Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, Clifford E. Cummings, SNUG-2001.

Clock Domain Crossing, A white paper from Cadence Design Systems, 2004.

Understanding Clock Domain Crossing Issues, EE Times, 2007

Verilog Nonblocking Assignments With Delays, Myths and Mysteries, Clifford E. Cummings, SNUG-2002.

Slides Used in Lecture
HDL Notes
Notes on synthesizable HDL coding approaches. Examples of how poor coding can lead to non-obvious results.
Effects of Clock Skew
Synchronous Memory Interface Timing

next up previous
Next: ECE532S Course Description Up: PC's Home
Paul Chow 2011-03-27