ECE341 Practice Question Website


Main Assembly Programming Input/Output Memory Computer Architecture Advanced Topics

Question 1

Computer Architecture Questions

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Question 1

Consider the architecture as shown and the following instruction:

link a6, #-8
Bus Architecture
Give the register transfer notation for all of the steps of the execution of this instruction. Assume that the operation of the instruction, the operand, all addresses and registers are 2 bytes long, that each memory fetch is two bytes, and that the CPU addresses bytes.

Answer

sp <- [sp] - 2;
[sp] <- [a6];
a6 <- [sp];
sp <- [sp] - 8;


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Question 2

Computer Architecture Questions

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Question 2

Consider the architecture as shown and the following instruction:

link a6, #-8
Bus Architecture
In the instruction, what does the “#-8” allocate space for (i.e., “#0” would not allocate any space for this)?

Answer

Local variables.


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Question 3

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Question 3

Consider the architecture as shown and the following instruction:

link a6, #-8
Bus Architechture
Give the steps and control signals for implementing this instruction using the table on the next page. Include the instruction fetch. Efficiency will be part of your mark on this question. Comments are optional, but may increase part marks---register transfer notation can be a helpful comment in this case. Use ONLY the following control signals:

IRin, PCin, PCout, Zin, Zout, Yin, MDRin, MDRout, ALUadd, ALUsub (subtract: bus value minus selected value), select Y, select 0, select 1, select 2, select 4, READ, WRITE, WMFC, END

Answer

Step Control Signals Comment
Step 1 PCout, MARin, READ, select 2, ALUadd, Zin,WMFC Fetch inst, inc PC
Step 2 Zout, PCin Fetch & inc
Step 3 WMFC, MDRout, IRin Fetch & inc
Step 4 A7out, select 2, ALUsub, Zin Z<-[a7]-2
Step 5 Zout, a7in, MARin A7<-[Z]
Step 6 A6out, MDRin, WRITE [A7]<-[A6]
Step 7 A7out, A6in, Yin [A6]<-[A7];Y<-A7
Step 8 WMFC, PCout, MARin, READ, select 2, ALUadd, Zin Z<-[[PC]] (fetch #-8, inc PC)
Step 9 Zout, PCin Inc PC
Step 10 WMFC MDRout, select Y, ALUadd, A7in, END A7<-[Y]+(#-8)


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Question 4

Computer Architecture Questions

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Question 4

This question assumes the machine architecture at the right. Note the stack pointer register, SP, is not part of the register file. SEL is a multiplexor used to select one of the inputs to the ALU.
Assume memory addresses require only one memory cycle to fetch or store (unlike the 68000). Bus Architechture

Show the machine code control sequence of the RTE (return from exception/interrupt) instruction as in the 68000 showing the register transfers at each step that implements the instruction. Include the instruction fetch sequence.

Answer

  1. WMFC, PCout, MARin, Read, Yin
  2. Sel2, Add, Zin
  3. Zout, PCin, [Yin]
  4. WMFC, MDRout, IRin
  5. SPout, MARin, Read,Yin
  6. Add, Zin, Sel 2
  7. WMFC, MDRout, STATUSin
  8. Zout, MARin, Yin, Read
  9. Add, Zin, Sel2
  10. Zout, SPin
  11. WMFC, MDRout, PCin, END



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Question 5

Computer Architecture Questions

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Question 5

This question assumes the machine architecture at the right. Note the stack pointer register, SP, is not part of the register file. SEL is a multiplexor used to select one of the inputs to the ALU.
Assume memory addresses require only one memory cycle to fetch or store (unlike the 68000). Bus Architechture

Show the machine code control sequence of an instruction that will set a block of from 1 to 127 memory locations to zero. The size of the block is in R0 and the address of the block is in R1. Assume the instruction fetch sequence is the same as in Question 4 and start with the next step. R0 and R1 can change in the execution of the sequence.

Answer

  1. Sel0, And, MDRin
  2. WMFC, R1out, MARin, WRITE, Yin
  3. Sel1, Add, Zin, R0out, Yin
  4. Zout, R1in, MARin, Sel1, Sub, Zin, IF Zero END else Goto step 6



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Question 6

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Question 6

Write a 68000 subroutine that sets a block of memory locations to zero where the size of the block (1 to 127) is in register d0 and the address of the block is in register a1. The register values can change in the subroutine.

Answer

 

Loop 	Moveq.b	#0,(a1)+
	dec.b 	d0
	bne 	Loop


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Question 7

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Question 7

The comment has been made that implementation of application-specific instructions in a processor can speed up an application by 20% to 1000%. Show how your results might support this comment based on analyses of your answers to Question 5 and Question 6.

Answer

The implementation of the instructions for the 68000 loop would be longer in machine code control sequences and the fetching of the instructions would take far more time.


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Question 8

Computer Architecture Questions

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Question 8

Consider the two-bus architecture shown, and the following instruction. 

add.w	d5,(a3)+
Give the register transfer notation for each of the two parts of this instruction (assume that a word is 2 bytes)

[a3]<-

a3<-

Answer

[a3]<-[[a3]]+d5

a3<-[a3]+2



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Question 9

Computer Architecture Questions

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Question 9

Consider the two-bus architecture shown, and the following instruction. 

add.w	d5,(a3)+
Give the steps and control signals for implementing the instruction in the table. Use ONLY the following control signals:

IRin, PCinA, PCinB, PCout, Zin, Zout, d5inA, d5inB, d5out, a3inA, a3inB, a3out, YinA, YinB,select Y, select 0, select 1, select2, MARinA, MARinB, MDRinA, MDRinB, MDRout, ALUadd, READ, WRITE, WMFC, END

10 places are provided for your answer – use only the steps you need

Step 1  
Step 2  
Step 3  
Step 4  
Step 5  
Step 6  
Step 7  
Step 8  
Step 9  
Step 10  

Answer

Step 1 WMFC, PCout, MARinA, READ, select 2, ALUadd, PCinB
Step 2 WMFC, MDRout, IRin
Step 3 a3out, MARinA, READ, select 2, ALUadd, a3inB
Step 4 d5out, YinA
Step 5 WMFC, select Y, MDRout, ALUadd, MDRinB, WRITE, END

This is the most efficient solution

SOLUTION NOTES:



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