The Transmogrifier-4 Project

TM-4 Photo

The Transmogrifier-4

The Transmogrifier-4, or TM-4 for short, is the latest in a series of configurable rapid prototyping systems with significant new capabilities. It has high memory capacity (8GBytes), high memory bandwidth (8 banks of 1Gbyte DDR SDRAM running at 133 Mhz DDR each) much higher host-bandwidth (on the order of 200 Mbytes/s) and high inter-chip bandwidth.

The TM-4 Architecture

The TM-4 contains four Altera Stratix EP1S80F1508C6 FPGA devices. Each of the four FPGAs is connected to each of the other through point-to-point buses. Each of these devices is also connected to two 1GB DDR SDRAM, an io-connector, and a development bus that allows communication with the housekeeping chip. The housekeeping chip provides communication, download, and control functions through the host single board computer. The housekeeping chip is not available to the user outside of the built-in functions. Video in/out functions are available on chip 0, and firewire is available on chip 1. The TM-4 also has 2 independently programmable globally synchronous clocks. Schematics are available to try to answer some of the details.

Complete design schematics of the TM-4 rev-A (pdf)

Development FPGA Interconnect

TM-4 Interconnect Structure


Global Clocks

The TM-4 contains 2 programmable board-wide globally-synchronous clocks. Each can be set at any frequency between 1-100Mhz, with 1Mhz steps. The resulting two clocks do not have a defined phase relationship. It is up to the user to generate phase related clocks through the use of on-FPGA PLLs.

The command for changing clock frequencies is:

% tm4 set_clk CLK_NO FREQ

where CLK_NO is the clock number from 0 to 1
and FREQ is frequency in hertz

Memory Clocks

Each of the DDR SDRAM modules require three sets of source synchronous clocks. These clocks must be generated by the PLLs within each FPGA. An example of this can be seen in the DDR SDRAM controller example circuit.

Video IO / Firewire Clocks

Each of the video peripherials has their own clocking requirements. They either drive a clock to the FPGA or require a clock to be generated from the FPGA.

Inter-FPGA source synchronous clocks

Each of the development FPGAs has three clock outputs, one for each of the other FPGAs, which can be used for source- synchronous inter-FPGA communication. These clocks are all delay matched with the corresponding inter-FPGA LVDS signals.


Each of the four Stratix chips is connected to two 1GB 133Mhz DDR SDRAM modules. The modules are ECC type, with a width of 72bits.

Information on how to use the DDR SDRAM memory of the TM-4 can be found here.


Video input and output devices are connected to fpga-0. The video devices available are: a NTSC video decoder and a video RAMDAC for the digital to RGB out conversion (VGA).

To enable the various video peripherals use the following commands:

Video out
%tm4 enable_video

Video In Channel A
%tm4 enable_video_in_a

Video In Channel B
%tm4 enable_video_in_b

More detailed information can be found here


Two identical Firewire interfaces are available on fpga-1.

Each interface has a Texas Instruments TSB12LV32 chip that serves two Firewire ports (for a grand total of 4).

More detailed information can be found here
A Firewire video interface is available here for capturing video from digital cameras.

Making things connect

Connecting your design to clocks, video, sram, or inter-FPGA signals is done automatically by just asking for the appropriate net name at the top level of your design. The TM-4 router (tm4gr) will do the rest.

Design entry

Creating and running designs is described HERE.
An example of a VHDL implementation can be found HERE.
Documentation of the ports package can be found HERE.
A description of how to interface with tm4mon can be found HERE.

Note: There are some issues in the way the global router parses the entity declarations in VHDL. Only one port can be declared on each line, and the first port declaration must be on its own line, not the same line as "entity blah is port(" . Additionally, the logic type of entity ports must be std_logic or std_logic_vector.

Running your design

simply enter the command

% tm4run

in your design directory

NOTE: your design directory must be world readable.


All of the required software for the TM-4 is located in ~tm4/bin. Example applications are located in ~tm4/examples. These examples are the best way to familurize yourself with the design flow of the TM-4.


There are a number of ways to debug your TM-4 design. You can use the "ports" package, jtag chain, or connect design signals to the I/O port and examine them with a logic analyzer.
To use the jtag features of the TM-4, use the command:

% tm4jtag

You can also use Quartus's SignalTap soft logic analyzer feature to debug your design. Each TM-4 machine has a Quartus jtagd server daemon running on it, which Quartus can use to talk to the FPGAs on the board. The password for each server is "54321".

Current Status

There are 4 TM-4 machines in LP392. They are all research prototypes, and they each have their own quirks. This is the current status of each machine as of October 2008:

crunch nyx wildcat cougar
Version TM-4 TM-4B TM-4B TM-4B
FPGAs 3 (fpga2 won't program) 4 4 4
PCI (ports package) reliability - reading from circuit poor poor good good
PCI (ports package) reliability - writing to circuit good good good good
PCI (ports package) speed - reading from circuit (Mbytes/sec) 5 8.9 2.8 5
PCI (ports package) speed - writing to circuit (Mbytes/sec) 4.8 17.4 17.4 16.7
DDR DIMMs 1A (fpga1, dimm A) and 3A good, all others flaky all 8 good 0A bad, all others good 0A, 1A and 3B bad, others good
VGA Quality good good good flaky
Communication between FPGAs bad poor good poor
Other Some FPGAs see more edges on tm4_glbclk* than the others do Won't boot - April 2009 Won't boot - April 2009

Ports Package Implementation on the Altera/Terasic DE-2 and DE-3

A preliminary attempt at porting the TM-4 ports package to the DE-2 and DE-3 development boards is available here.