ECE1373S: VLSI Systems Design
For a purely behavioural model.
OK RTL VHDL
Should synthesize to a reasonable circuit.
A Synopsys netlist of the adder resulting from synthesis of the above circuit.
Bad VHDL for Synthesis
This will not synthesize!
Mealy FSM in Verilog
Verilog example of a FSM that should synthesize okay.
Moore FSM in Verilog
Another Verilog example of a FSM that should synthesize okay.
This is a simple example illustrating good design practices. You should study it and emulate it!
Notes and Handouts
VHDL Slides by Sean Peng
Pins to Verilog flow
FPGA Design and Verification flow
Custom and ASIC flows
Sample directory structure
505 Registers or Bust, a paper by Wilson Snyder
Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, a paper by Cliff Cummings
Requirements and Report Format
Paul Chow 2005-02-07