ECE1749H - Interconnection Networks for Parallel Computer Architectures

Spring 2011
Department of Electrical and Computer Engineering
University of Toronto

Instructor:
Prof. Natalie Enright Jerger
MAIN | COURSE OUTLINE | PROJECT | READINGS

Course Outline

Update: Project Reminders posted for April 6 class.

Update: No Class on Feb 2. Class will be extended 1 extra week in April to make up the Feb 2 class.

Presenters updated.
Update: Updated notes for Jan 12, 2011 class.
Course Notes from 2010 offering - will be updated as the semester progresses

DateTopics ReadingPresenter
Check back for updates		 Assignment
January 12, 2011 Introduction,
 Chapter 1:[1up][3up] (updated Jan 12, 2011)
 --
January 19, 2011 System Interfaces
Topology
 Chapter 2
Chapter 3
 --
January 26, 2011 Topology,
Discussion of Project Topics		 1. Flattened Butterfly Topology for On-Chip Networks PDF
2. Performance Analysis of k-ary n-cubes PDF
3. Design and Evaluation of a Hierarchical On-Chip Interconnect
for Next-Generation CMPs PDF
4. Express Cube Topologies for On-Chip Networks PDF
 1. Jasmina Vasiljevic (Flattened Butterfly)
2. Hao Jun (Express Cube)
 Critique of 1 Paper due
(see Readings for details)
February 2, 2011 Cancelled Project Proposals due
February 9, 2011 Routing Chapter 4 (Updated Feb 9, 2011)
 --
February 16, 2011 Routing Algorithms 1. Near optimal worst-case throughput routing for two-dimensional mesh networks PDF
2. Recursive Partitioning Multicast: A Bandwidth-Efficient Routing for
Networks-on-Chip PDF
3. Deadlock-Free Adaptive Routing PDF
4. Regional Congestion Awareness for Load Balance in Networks on Chip PDF
 1. Harsh Singh (Regional)
2. Tony Feng (Recursive)
Critique of 1 paper due
February 23, 2011 Reading Week - No class
March 2, 2011 Flow Control Chapter 5: [1UP][3UP][PPT]
 --
March 9, 2011 Flow Control 1. Elastic-Buffer Flow Control for On-Chip Networks PDF
2. Express Virtual Channels: Toward the ideal interconnection fabric
PDF
3. ViCHar: A Dynamic Virtual Channel Regulator for Network-on-Chip
Routers PDF
4. Virtual-Channel Flow Control PDF
 1. Islam Atta (Elastic-Buffer)
2. Yu Han (Express Virtual Channels)
 Project Progress Report due
Critique of 1 paper due
March 16, 2011 Router Microarchitecture Chapter 6: [PPTX][PPT][PDF] --
March 23, 2011 Router Microarchitecture 1. Low-Latency Virtual-Channel Routers for On-Chip
Networks PDF
2. Low-Cost Router Microarchitecture PDF
3. Microarchitecture of a High-Radix Router PDF
4. The Alpha 21364 network architecture PDF
 1. Goran Narancic (Low-Cost)
2. Peter Ng (High-Radix)
Critique of 1 paper due
March 30, 2011 Systems 1. Intel SCC PDF
2. Characterizing the Cell EIB On-Chip Network PDF
3. On-Chip Interconnection Architecture of the Tile Processor PDF
 1. Vincent Mirian (Tile Processor)
2. Mike Delorme (SCC)
Critique of 1 paper due
April 6, 2011 Potpourri
Announcements		 1. Power-driven Design of Router Microarchitectures in On-chip Networks PDF
2. A Case for Dynamic Frequency Tuning in On-Chip Networks PDF
3. Corona: System Implications of Emerging Nanophotonic
Technology PDF
4. Aergia: Exploiting Packet Latency Slack in On-Chip Networks PDF
 1. Sayed-Ali Shariatmadari (Dynamic Frequency Tuning)
 Critique of 1 paper due
April 13, 2011 Project Presentations -- -- Final Project Report due April 22, 2011
Last modified: Wed Apr 6 12:09:38 EDT 2011